{"id":"https://openalex.org/W3048489956","doi":"https://doi.org/10.1109/vlsicircuits18222.2020.9162955","title":"A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL","display_name":"A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL","publication_year":2020,"publication_date":"2020-06-01","ids":{"openalex":"https://openalex.org/W3048489956","doi":"https://doi.org/10.1109/vlsicircuits18222.2020.9162955","mag":"3048489956"},"language":"en","primary_location":{"id":"doi:10.1109/vlsicircuits18222.2020.9162955","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsicircuits18222.2020.9162955","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040477650","display_name":"Yuncheng Zhang","orcid":"https://orcid.org/0000-0001-6467-3667"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Yuncheng Zhang","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045260163","display_name":"Bangan Liu","orcid":"https://orcid.org/0000-0002-3535-2407"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Bangan Liu","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019873981","display_name":"Xiaofan Gu","orcid":"https://orcid.org/0000-0002-2989-8278"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Xiaofan Gu","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031175011","display_name":"Wang Chun","orcid":"https://orcid.org/0000-0001-6994-0146"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Chun Wang","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044137703","display_name":"Kiyoshi Yanagisawa","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kiyoshi Yanagisawa","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068137637","display_name":"Junjun Qiu","orcid":"https://orcid.org/0000-0002-3698-4369"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Junjun Qiu","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088122376","display_name":"Yun Wang","orcid":"https://orcid.org/0000-0001-7773-1619"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yun Wang","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085361118","display_name":"Jian Pang","orcid":"https://orcid.org/0000-0002-6278-6294"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Jian Pang","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028333708","display_name":"Atsushi Shirane","orcid":"https://orcid.org/0000-0001-8172-4323"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsushi Shirane","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064086312","display_name":"Kenichi Okada","orcid":"https://orcid.org/0000-0002-1082-7672"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenichi Okada","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5040477650"],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":0.411,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.61129061,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.8677477836608887},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.833732008934021},{"id":"https://openalex.org/keywords/spur","display_name":"Spur","score":0.7153207063674927},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6378703117370605},{"id":"https://openalex.org/keywords/polar","display_name":"Polar","score":0.5113663077354431},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5010077953338623},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.4843834340572357},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4700697064399719},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4689571261405945},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.46165502071380615},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44757795333862305},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4259393811225891},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3700101971626282},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.29221153259277344},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2694808542728424},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.16965079307556152}],"concepts":[{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.8677477836608887},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.833732008934021},{"id":"https://openalex.org/C2779821383","wikidata":"https://www.wikidata.org/wiki/Q7581537","display_name":"Spur","level":2,"score":0.7153207063674927},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6378703117370605},{"id":"https://openalex.org/C29705727","wikidata":"https://www.wikidata.org/wiki/Q294562","display_name":"Polar","level":2,"score":0.5113663077354431},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5010077953338623},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.4843834340572357},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4700697064399719},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4689571261405945},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.46165502071380615},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44757795333862305},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4259393811225891},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3700101971626282},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.29221153259277344},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2694808542728424},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.16965079307556152},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsicircuits18222.2020.9162955","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsicircuits18222.2020.9162955","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8799999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2359366503","https://openalex.org/W2375072050","https://openalex.org/W2376731877","https://openalex.org/W2330020385","https://openalex.org/W3145870900","https://openalex.org/W2371350995","https://openalex.org/W1973484824","https://openalex.org/W2110035284","https://openalex.org/W2007789933","https://openalex.org/W2161157531"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,34,75,85],"power-efficient":[4],"digital":[5],"polar":[6,18],"transmitter":[7,19,69],"using":[8],"1.5bit-DSM-based":[9],"Class-D":[10],"PA":[11],"and":[12,51,65,84],"fractional-N":[13],"injection-locked":[14],"PLL.":[15],"The":[16,43,68],"DSM-based":[17],"can":[20],"avoid":[21],"redundant":[22],"charge/discharge":[23],"of":[24,77,82,88],"turned-off":[25],"transistors":[26],"in":[27,37,71],"the":[28,48,59,63,66],"conventional":[29],"SCPA,":[30],"which":[31],"contributes":[32],"to":[33,57],"drastic":[35],"improvement":[36],"power":[38,41],"efficiency":[39,87],"at":[40,79],"back-off.":[42],"PLL":[44],"is":[45,54],"used":[46],"as":[47],"phase":[49],"modulator,":[50],"spur-mitigation":[52],"technique":[53],"also":[55],"applied":[56],"minimizes":[58],"frequency":[60],"mismatch":[61],"between":[62],"oscillator":[64],"reference.":[67],"implemented":[70],"65nm":[72],"CMOS":[73],"achieves":[74],"PAE":[76],"29%":[78],"an":[80],"EVM":[81],"-25.1dB,":[83],"system":[86],"21.7%.":[89]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
