{"id":"https://openalex.org/W3048835745","doi":"https://doi.org/10.1109/vlsicircuits18222.2020.9162782","title":"A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV V<sub>MIN</sub> Reduction with Negligible Power Overhead","display_name":"A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV V<sub>MIN</sub> Reduction with Negligible Power Overhead","publication_year":2020,"publication_date":"2020-06-01","ids":{"openalex":"https://openalex.org/W3048835745","doi":"https://doi.org/10.1109/vlsicircuits18222.2020.9162782","mag":"3048835745"},"language":"en","primary_location":{"id":"doi:10.1109/vlsicircuits18222.2020.9162782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsicircuits18222.2020.9162782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007891380","display_name":"Zheng Guo","orcid":"https://orcid.org/0000-0001-8615-9749"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheng Guo","raw_affiliation_strings":["Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041500446","display_name":"Jami Wiedemer","orcid":"https://orcid.org/0000-0001-6874-0636"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jami Wiedemer","raw_affiliation_strings":["Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101688825","display_name":"Yusung Kim","orcid":"https://orcid.org/0000-0002-4051-3789"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yusung Kim","raw_affiliation_strings":["Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057737162","display_name":"Prithvee Sundararajan Ramamoorthy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prithvee Sundararajan Ramamoorthy","raw_affiliation_strings":["Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027136443","display_name":"Prateeksha Bindiganavile Sathyaprasad","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prateeksha Bindiganavile Sathyaprasad","raw_affiliation_strings":["Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082155409","display_name":"Smita Shridharan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Smita Shridharan","raw_affiliation_strings":["Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100644921","display_name":"Daeyeon Kim","orcid":"https://orcid.org/0000-0002-5879-8313"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daeyeon Kim","raw_affiliation_strings":["Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053857493","display_name":"Eric Karl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric Karl","raw_affiliation_strings":["Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.3578,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.44841481,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.8139749765396118},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7525337934494019},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6326395273208618},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6090283393859863},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45998305082321167},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42222753167152405},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3579109013080597},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3305944800376892},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2927708327770233},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2332458794116974},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22140294313430786},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12116006016731262}],"concepts":[{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.8139749765396118},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7525337934494019},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6326395273208618},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6090283393859863},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45998305082321167},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42222753167152405},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3579109013080597},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3305944800376892},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2927708327770233},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2332458794116974},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22140294313430786},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12116006016731262},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsicircuits18222.2020.9162782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsicircuits18222.2020.9162782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8100000023841858,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W2109451123","https://openalex.org/W4378977321","https://openalex.org/W1976168335","https://openalex.org/W3211992815","https://openalex.org/W179354024"],"abstract_inverted_index":{"A":[0],"21Mb/mm2SRAM":[1],"design":[2],"using":[3],"0.0367um2HCC":[4],"bitcell":[5],"on":[6],"a":[7,42],"10nm":[8],"CMOS":[9],"technology":[10],"is":[11,18,32],"presented.":[12],"Gate-modulated":[13],"self-collapse":[14],"(GSC)":[15],"write":[16],"assist":[17],"utilized":[19],"to":[20,34],"enable":[21],"175mV":[22],"reduction":[23],"in":[24,41],"VMINwith":[25],"minimal":[26],"energy":[27],"overhead.":[28],"Instance":[29],"area":[30],"overhead":[31],"limited":[33],"3-5%":[35],"by":[36],"implementing":[37],"the":[38],"GSC":[39],"circuitry":[40],"row-based":[43],"configuration":[44],"with":[45],"modified":[46],"SRAM":[47],"bitcells.":[48]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}