{"id":"https://openalex.org/W3048803445","doi":"https://doi.org/10.1109/vlsicircuits18222.2020.9162779","title":"315-GHz Self-Synchronizing Minimum Shift Keying Receiver in 65-nm CMOS","display_name":"315-GHz Self-Synchronizing Minimum Shift Keying Receiver in 65-nm CMOS","publication_year":2020,"publication_date":"2020-06-01","ids":{"openalex":"https://openalex.org/W3048803445","doi":"https://doi.org/10.1109/vlsicircuits18222.2020.9162779","mag":"3048803445"},"language":"en","primary_location":{"id":"doi:10.1109/vlsicircuits18222.2020.9162779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsicircuits18222.2020.9162779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055548726","display_name":"Ibukunoluwa Momson","orcid":"https://orcid.org/0000-0001-5983-4489"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ibukunoluwa Momson","raw_affiliation_strings":["Texas Analog Center of Excellence and Department of ECE, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Analog Center of Excellence and Department of ECE, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058727360","display_name":"Shenggang Dong","orcid":"https://orcid.org/0000-0002-4530-5065"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shenggang Dong","raw_affiliation_strings":["Texas Analog Center of Excellence and Department of ECE, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Analog Center of Excellence and Department of ECE, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036379526","display_name":"Pavan Yelleswarapu","orcid":"https://orcid.org/0000-0001-5605-417X"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pavan Yelleswarapu","raw_affiliation_strings":["Texas Analog Center of Excellence and Department of ECE, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Analog Center of Excellence and Department of ECE, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080735730","display_name":"Wooyeol Choi","orcid":"https://orcid.org/0000-0002-6248-0674"},"institutions":[{"id":"https://openalex.org/I115475287","display_name":"Oklahoma State University","ror":"https://ror.org/01g9vbr38","country_code":"US","type":"education","lineage":["https://openalex.org/I115475287"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wooyeol Choi","raw_affiliation_strings":["Oklahoma State University, Stillwater, OK, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Oklahoma State University, Stillwater, OK, USA","institution_ids":["https://openalex.org/I115475287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025240967","display_name":"Kenneth K. O","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. O. Kenneth","raw_affiliation_strings":["Texas Analog Center of Excellence and Department of ECE, The University of Texas at Dallas, Richardson, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Analog Center of Excellence and Department of ECE, The University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6244,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.68182918,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10796","display_name":"Cooperative Communication and Network Coding","score":0.9815000295639038,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/synchronizing","display_name":"Synchronizing","score":0.9385011792182922},{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.7903634905815125},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5964508056640625},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5933097004890442},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5389062166213989},{"id":"https://openalex.org/keywords/on-off-keying","display_name":"On-off keying","score":0.5258693695068359},{"id":"https://openalex.org/keywords/minimum-shift-keying","display_name":"Minimum-shift keying","score":0.5231536626815796},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5182973742485046},{"id":"https://openalex.org/keywords/keying","display_name":"Keying","score":0.500882625579834},{"id":"https://openalex.org/keywords/radio-receiver-design","display_name":"Radio receiver design","score":0.4808555245399475},{"id":"https://openalex.org/keywords/phase-shift-keying","display_name":"Phase-shift keying","score":0.463625431060791},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4400351941585541},{"id":"https://openalex.org/keywords/equalization","display_name":"Equalization (audio)","score":0.4261247515678406},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.42452287673950195},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.33549755811691284},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3108102083206177},{"id":"https://openalex.org/keywords/bit-error-rate","display_name":"Bit error rate","score":0.2638564705848694},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.20773738622665405},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.19599005579948425}],"concepts":[{"id":"https://openalex.org/C162932704","wikidata":"https://www.wikidata.org/wiki/Q1058791","display_name":"Synchronizing","level":3,"score":0.9385011792182922},{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.7903634905815125},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5964508056640625},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5933097004890442},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5389062166213989},{"id":"https://openalex.org/C170030856","wikidata":"https://www.wikidata.org/wiki/Q1136128","display_name":"On-off keying","level":5,"score":0.5258693695068359},{"id":"https://openalex.org/C55857970","wikidata":"https://www.wikidata.org/wiki/Q4156818","display_name":"Minimum-shift keying","level":5,"score":0.5231536626815796},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5182973742485046},{"id":"https://openalex.org/C2776542216","wikidata":"https://www.wikidata.org/wiki/Q6398306","display_name":"Keying","level":2,"score":0.500882625579834},{"id":"https://openalex.org/C175291425","wikidata":"https://www.wikidata.org/wiki/Q7281193","display_name":"Radio receiver design","level":4,"score":0.4808555245399475},{"id":"https://openalex.org/C186378180","wikidata":"https://www.wikidata.org/wiki/Q4874866","display_name":"Phase-shift keying","level":4,"score":0.463625431060791},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4400351941585541},{"id":"https://openalex.org/C75755367","wikidata":"https://www.wikidata.org/wiki/Q104531076","display_name":"Equalization (audio)","level":3,"score":0.4261247515678406},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.42452287673950195},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.33549755811691284},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3108102083206177},{"id":"https://openalex.org/C56296756","wikidata":"https://www.wikidata.org/wiki/Q840922","display_name":"Bit error rate","level":3,"score":0.2638564705848694},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.20773738622665405},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.19599005579948425}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsicircuits18222.2020.9162779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsicircuits18222.2020.9162779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7699999809265137,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2068360072"],"related_works":["https://openalex.org/W1555536746","https://openalex.org/W2017769333","https://openalex.org/W1489774986","https://openalex.org/W2058692089","https://openalex.org/W4387012388","https://openalex.org/W2540445693","https://openalex.org/W2373332278","https://openalex.org/W2611968102","https://openalex.org/W2018458992","https://openalex.org/W2990380363"],"abstract_inverted_index":{"A":[0],"self-synchronizing":[1,83],"minimum":[2],"shift":[3],"keying":[4],"(MSK)":[5],"receiver":[6,17,41],"operating":[7],"at":[8,56],"315-GHz":[9,38,77],"RF":[10,58,78],"is":[11,42,79],"demonstrated":[12],"in":[13,32],"65-nm":[14],"CMOS.":[15],"The":[16,40,76],"outputs":[18],"digital":[19],"bits":[20],"and":[21,71,73,85],"utilizes":[22],"a":[23,29,46],"PLL":[24],"based":[25],"architecture":[26],"that":[27],"includes":[28],"frequency":[30,66],"doubler":[31],"the":[33,37,69,80],"loop":[34],"to":[35,44],"achieve":[36],"operation.":[39],"used":[43],"form":[45],"10-Gbps":[47],"link":[48],"with":[49],"BER":[50],"<;":[51],"10":[52],"<sup":[53],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[54],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">-11</sup>":[55],"an":[57],"input":[59],"power":[60],"of":[61],"-21-dBm":[62],"without":[63],"using":[64],"separate":[65],"synchronization":[67],"between":[68],"transmitter":[70],"receiver,":[72],"data":[74],"equalization.":[75],"highest":[81],"for":[82,86],"receivers":[84],"MSK":[87],"receivers.":[88]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}