{"id":"https://openalex.org/W2899092733","doi":"https://doi.org/10.1109/vlsic.2018.8502278","title":"A 14 \u00b5M \u00d7 26 \u00b5M 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance","display_name":"A 14 \u00b5M \u00d7 26 \u00b5M 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2899092733","doi":"https://doi.org/10.1109/vlsic.2018.8502278","mag":"2899092733"},"language":"en","primary_location":{"id":"doi:10.1109/vlsic.2018.8502278","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2018.8502278","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023124977","display_name":"Long Kong","orcid":"https://orcid.org/0000-0002-6568-3071"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Long Kong","raw_affiliation_strings":["Electrical Engineering Department, University of California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100748025","display_name":"Yikun Chang","orcid":"https://orcid.org/0000-0001-9314-7332"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yikun Chang","raw_affiliation_strings":["Electrical Engineering Department, University of California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049567991","display_name":"Behzad Razavi","orcid":"https://orcid.org/0000-0003-1168-9205"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Behzad Razavi","raw_affiliation_strings":["Electrical Engineering Department, University of California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"271","last_page":"272"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9379678964614868},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.6415971517562866},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6101363897323608},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5483938455581665},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.518932580947876},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.5062664747238159},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.4862164556980133},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4225127696990967},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3579358756542206},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.333451509475708},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.3068395256996155},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20465433597564697},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1916739046573639},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15976828336715698}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9379678964614868},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.6415971517562866},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6101363897323608},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5483938455581665},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.518932580947876},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.5062664747238159},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.4862164556980133},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4225127696990967},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3579358756542206},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.333451509475708},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.3068395256996155},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20465433597564697},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1916739046573639},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15976828336715698}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsic.2018.8502278","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2018.8502278","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Symposium on VLSI Circuits","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2070109416","https://openalex.org/W1523213765","https://openalex.org/W2040399070","https://openalex.org/W2388316590","https://openalex.org/W2121182846","https://openalex.org/W4388486464","https://openalex.org/W2089131288","https://openalex.org/W2111818678","https://openalex.org/W2743705867","https://openalex.org/W86332949"],"abstract_inverted_index":{"A":[0],"full-rate":[1],"CDR":[2],"loop":[3],"employs":[4],"a":[5,9,15,19,22,27,40,50],"3-stage":[6],"ring":[7],"VCO,":[8],"master-slave":[10],"passive":[11],"sampler":[12],"as":[13],"both":[14],"phase":[16],"detector":[17],"and":[18,21,49],"filter,":[20],"new":[23],"flipflop":[24],"to":[25],"achieve":[26],"bandwidth":[28],"of":[29,43,54],"170":[30],"MHz.":[31],"Implemented":[32],"in":[33],"45-nm":[34],"CMOS":[35],"technology,":[36],"the":[37],"circuit":[38],"exhibits":[39],"jitter":[41,53],"tolerance":[42],"2":[44,58],"UI":[45],"at":[46],"5":[47],"MHz":[48],"recovered":[51],"clock":[52],"340":[55],"fs":[56],"with":[57],"<sup":[59],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[60],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">7</sup>":[61],"-1":[62],"PRBS.":[63]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}