{"id":"https://openalex.org/W2524250502","doi":"https://doi.org/10.1109/vlsic.2016.7573510","title":"A field-programmable mixed-signal IC with time-domain configurable analog blocks","display_name":"A field-programmable mixed-signal IC with time-domain configurable analog blocks","publication_year":2016,"publication_date":"2016-06-01","ids":{"openalex":"https://openalex.org/W2524250502","doi":"https://doi.org/10.1109/vlsic.2016.7573510","mag":"2524250502"},"language":"en","primary_location":{"id":"doi:10.1109/vlsic.2016.7573510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2016.7573510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068334464","display_name":"Yunju Choi","orcid":"https://orcid.org/0000-0002-6445-5202"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Yunju Choi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Seoul National University, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Seoul National University, Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102784518","display_name":"Yoontaek Lee","orcid":"https://orcid.org/0000-0001-9319-2889"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yoontaek Lee","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Seoul National University, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Seoul National University, Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059067053","display_name":"Seung\u2010heon Chris Baek","orcid":"https://orcid.org/0000-0003-1338-8238"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seung-Heon Baek","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Seoul National University, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Seoul National University, Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056138393","display_name":"Sung\u2010Joon Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sung-Joon Lee","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Seoul National University, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Seoul National University, Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015393579","display_name":"Jaeha Kim","orcid":"https://orcid.org/0000-0003-2237-3134"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaeha Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Seoul National University, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Seoul National University, Korea","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5068334464"],"corresponding_institution_ids":["https://openalex.org/I139264467"],"apc_list":null,"apc_paid":null,"fwci":0.3675,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.66143573,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7234073877334595},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6515583992004395},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.607423722743988},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5431624054908752},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.52309250831604},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4985673427581787},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4839742183685303},{"id":"https://openalex.org/keywords/pulse-width-modulation","display_name":"Pulse-width modulation","score":0.4516928195953369},{"id":"https://openalex.org/keywords/analog-signal-processing","display_name":"Analog signal processing","score":0.4412953555583954},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4315900504589081},{"id":"https://openalex.org/keywords/time-domain","display_name":"Time domain","score":0.415131539106369},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.3656708002090454},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32703498005867004},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3236270248889923},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3079737424850464},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30399972200393677},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.2619451880455017},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13233539462089539}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7234073877334595},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6515583992004395},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.607423722743988},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5431624054908752},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.52309250831604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4985673427581787},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4839742183685303},{"id":"https://openalex.org/C92746544","wikidata":"https://www.wikidata.org/wiki/Q585184","display_name":"Pulse-width modulation","level":3,"score":0.4516928195953369},{"id":"https://openalex.org/C379707","wikidata":"https://www.wikidata.org/wiki/Q2328303","display_name":"Analog signal processing","level":4,"score":0.4412953555583954},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4315900504589081},{"id":"https://openalex.org/C103824480","wikidata":"https://www.wikidata.org/wiki/Q185889","display_name":"Time domain","level":2,"score":0.415131539106369},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.3656708002090454},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32703498005867004},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3236270248889923},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3079737424850464},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30399972200393677},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.2619451880455017},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13233539462089539},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsic.2016.7573510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2016.7573510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6200000047683716}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W115888153","https://openalex.org/W1585429535","https://openalex.org/W2774445564","https://openalex.org/W2229324318","https://openalex.org/W1591963733","https://openalex.org/W2060224337","https://openalex.org/W2116226449","https://openalex.org/W2531287736"],"abstract_inverted_index":{"A":[0],"field-programmable":[1],"mixed-signal":[2,10],"IC":[3,15,49],"for":[4],"fast-prototyping":[5],"and":[6,78],"low-cost":[7],"production":[8],"of":[9],"system":[11],"is":[12],"presented.":[13],"The":[14,47],"contains":[16],"time-domain":[17],"configurable":[18],"analog":[19],"blocks":[20],"(TCABs)":[21],"that":[22],"can":[23],"be":[24],"programmed":[25],"into":[26],"a":[27,63],"time-to-digital":[28],"converter":[29,81],"(TDC),":[30],"digitally":[31,35],"controlled":[32,36],"oscillator":[33],"(DCO),":[34],"delay":[37],"element,":[38],"digital":[39],"pulse-width":[40],"modulator":[41],"(DPWM),":[42],"or":[43],"phase":[44],"interpolator":[45],"(PI).":[46],"prototype":[48],"fabricated":[50],"in":[51],"65-nm":[52],"CMOS":[53],"demonstrates":[54],"its":[55],"versatile":[56],"programmability":[57],"with":[58,66,75,82],"the":[59],"successful":[60],"operations":[61],"as":[62],"1-GHz":[64],"PLL":[65],"12.3-ps":[67],"<sub":[68],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[69],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">rms</sub>":[70],"integrated":[71],"jitter,":[72],"50-MS/s":[73],"ADC":[74],"32.5-dB":[76],"SNDR,":[77],"1.2-to-0.7V":[79],"DC-DC":[80],"95.5%":[83],"efficiency.":[84]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}