{"id":"https://openalex.org/W2155294410","doi":"https://doi.org/10.1109/vlsic.2012.6243845","title":"A 3-stage Pseudo Single-phase Flip-flop family","display_name":"A 3-stage Pseudo Single-phase Flip-flop family","publication_year":2012,"publication_date":"2012-06-01","ids":{"openalex":"https://openalex.org/W2155294410","doi":"https://doi.org/10.1109/vlsic.2012.6243845","mag":"2155294410"},"language":"en","primary_location":{"id":"doi:10.1109/vlsic.2012.6243845","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2012.6243845","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Symposium on VLSI Circuits (VLSIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068048125","display_name":"H. Partovi","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Hamid Partovi","raw_affiliation_strings":["Veloce Technologies, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Veloce Technologies, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113503476","display_name":"Alfred Yeung","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alfred Yeung","raw_affiliation_strings":["Veloce Technologies, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Veloce Technologies, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028192239","display_name":"L. Ravezzi","orcid":"https://orcid.org/0000-0003-2427-6311"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Luca Ravezzi","raw_affiliation_strings":["Veloce Technologies, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Veloce Technologies, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090469068","display_name":"Mark Horowitz","orcid":"https://orcid.org/0000-0003-3245-7542"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Horowitz","raw_affiliation_strings":["University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5068048125"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7365,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.7584687,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"14","issue":null,"first_page":"172","last_page":"173"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11392","display_name":"Energy Harvesting in Wireless Networks","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.8709527850151062},{"id":"https://openalex.org/keywords/master/slave","display_name":"Master/slave","score":0.7038920521736145},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6323559880256653},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6044661998748779},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.549410879611969},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5306963324546814},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.4674677848815918},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4168429970741272},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3797006607055664},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2744095027446747},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2568258047103882},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.1700448989868164},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.14681050181388855}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.8709527850151062},{"id":"https://openalex.org/C20454292","wikidata":"https://www.wikidata.org/wiki/Q735523","display_name":"Master/slave","level":2,"score":0.7038920521736145},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6323559880256653},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6044661998748779},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.549410879611969},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5306963324546814},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.4674677848815918},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4168429970741272},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3797006607055664},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2744095027446747},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2568258047103882},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.1700448989868164},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.14681050181388855},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsic.2012.6243845","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2012.6243845","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Symposium on VLSI Circuits (VLSIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1575732703","https://openalex.org/W2068343640","https://openalex.org/W2107495642","https://openalex.org/W2137616964","https://openalex.org/W2138134203","https://openalex.org/W6680235823"],"related_works":["https://openalex.org/W2262031297","https://openalex.org/W1872078991","https://openalex.org/W2024069812","https://openalex.org/W2056378213","https://openalex.org/W2045056374","https://openalex.org/W2298981088","https://openalex.org/W2163601309","https://openalex.org/W2109195618","https://openalex.org/W2155294410","https://openalex.org/W4398219858"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,34,45,66],"energy-efficient":[4],"3-stage":[5],"Pseudo":[6],"Single-phase":[7],"family":[8],"of":[9,68,81],"Flip-flops":[10],"(PSPFF)":[11],"targeted":[12],"for":[13],"use":[14],"in":[15,19,27,72,79],"a":[16,20],"3GHz":[17],"microprocessor":[18],"40nm,":[21],"0.9V":[22],"CMOS":[23],"technology.":[24],"With":[25],"latencies":[26],"line":[28],"with":[29],"the":[30,40,56,59,77,82],"fast":[31],"pulsed-latch":[32,57],"and":[33,52,58],"average":[35],"switching":[36],"energy":[37],"comparable":[38],"to":[39],"master-slave":[41,60,83],"flip-flop,":[42],"PSPFF":[43,78],"achieves":[44],"energy-delay":[46],"product":[47],"(EDP)":[48],"which":[49],"is":[50],"42%":[51],"24%":[53],"lower":[54],"than":[55],"flip-flop":[61],"respectively.":[62],"Measurement":[63],"results":[64],"confirm":[65],"improvement":[67],"at":[69],"least":[70],"300MHz":[71],"operating":[73],"frequency":[74],"when":[75],"using":[76],"place":[80],"flip-flop.":[84]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}