{"id":"https://openalex.org/W2087632825","doi":"https://doi.org/10.1109/vlsic.2012.6243830","title":"A clock jitter reduction circuit using gated phase blending between self-delayed clock edges","display_name":"A clock jitter reduction circuit using gated phase blending between self-delayed clock edges","publication_year":2012,"publication_date":"2012-06-01","ids":{"openalex":"https://openalex.org/W2087632825","doi":"https://doi.org/10.1109/vlsic.2012.6243830","mag":"2087632825"},"language":"en","primary_location":{"id":"doi:10.1109/vlsic.2012.6243830","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2012.6243830","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Symposium on VLSI Circuits (VLSIC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056677721","display_name":"Kiichi Niitsu","orcid":"https://orcid.org/0000-0002-3813-3955"},"institutions":[{"id":"https://openalex.org/I165735259","display_name":"Gunma University","ror":"https://ror.org/046fm7598","country_code":"JP","type":"education","lineage":["https://openalex.org/I165735259"]},{"id":"https://openalex.org/I258063972","display_name":"Kiryu University","ror":"https://ror.org/02snehe53","country_code":"JP","type":"education","lineage":["https://openalex.org/I258063972"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kiichi Niitsu","raw_affiliation_strings":["Gunma University, Kiryu, Japan","Gunma University Kiryu Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Gunma University, Kiryu, Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]},{"raw_affiliation_string":"Gunma University Kiryu Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089541278","display_name":"Naohiro Harigai","orcid":null},"institutions":[{"id":"https://openalex.org/I165735259","display_name":"Gunma University","ror":"https://ror.org/046fm7598","country_code":"JP","type":"education","lineage":["https://openalex.org/I165735259"]},{"id":"https://openalex.org/I258063972","display_name":"Kiryu University","ror":"https://ror.org/02snehe53","country_code":"JP","type":"education","lineage":["https://openalex.org/I258063972"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Naohiro Harigai","raw_affiliation_strings":["Gunma University, Kiryu, Japan","Gunma University Kiryu Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Gunma University, Kiryu, Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]},{"raw_affiliation_string":"Gunma University Kiryu Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031069725","display_name":"Daiki Hirabayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I165735259","display_name":"Gunma University","ror":"https://ror.org/046fm7598","country_code":"JP","type":"education","lineage":["https://openalex.org/I165735259"]},{"id":"https://openalex.org/I258063972","display_name":"Kiryu University","ror":"https://ror.org/02snehe53","country_code":"JP","type":"education","lineage":["https://openalex.org/I258063972"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Daiki Hirabayashi","raw_affiliation_strings":["Gunma University, Kiryu, Japan","Gunma University Kiryu Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Gunma University, Kiryu, Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]},{"raw_affiliation_string":"Gunma University Kiryu Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081575023","display_name":"Daiki Oki","orcid":null},"institutions":[{"id":"https://openalex.org/I165735259","display_name":"Gunma University","ror":"https://ror.org/046fm7598","country_code":"JP","type":"education","lineage":["https://openalex.org/I165735259"]},{"id":"https://openalex.org/I258063972","display_name":"Kiryu University","ror":"https://ror.org/02snehe53","country_code":"JP","type":"education","lineage":["https://openalex.org/I258063972"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Daiki Oki","raw_affiliation_strings":["Gunma University, Kiryu, Japan","Gunma University Kiryu Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Gunma University, Kiryu, Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]},{"raw_affiliation_string":"Gunma University Kiryu Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067347468","display_name":"Masato Sakurai","orcid":"https://orcid.org/0000-0001-9296-3952"},"institutions":[{"id":"https://openalex.org/I165735259","display_name":"Gunma University","ror":"https://ror.org/046fm7598","country_code":"JP","type":"education","lineage":["https://openalex.org/I165735259"]},{"id":"https://openalex.org/I258063972","display_name":"Kiryu University","ror":"https://ror.org/02snehe53","country_code":"JP","type":"education","lineage":["https://openalex.org/I258063972"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masato Sakurai","raw_affiliation_strings":["Gunma University, Kiryu, Japan","Gunma University Kiryu Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Gunma University, Kiryu, Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]},{"raw_affiliation_string":"Gunma University Kiryu Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019563893","display_name":"Osamu Kobayashi","orcid":"https://orcid.org/0000-0001-8037-4624"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Osamu Kobayashi","raw_affiliation_strings":["STARC, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STARC, Yokohama, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010763159","display_name":"Takahiro Yamaguchi","orcid":"https://orcid.org/0000-0003-0325-8878"},"institutions":[{"id":"https://openalex.org/I165735259","display_name":"Gunma University","ror":"https://ror.org/046fm7598","country_code":"JP","type":"education","lineage":["https://openalex.org/I165735259"]},{"id":"https://openalex.org/I258063972","display_name":"Kiryu University","ror":"https://ror.org/02snehe53","country_code":"JP","type":"education","lineage":["https://openalex.org/I258063972"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takahiro J. Yamaguchi","raw_affiliation_strings":["Gunma University, Kiryu, Japan","Gunma University Kiryu Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Gunma University, Kiryu, Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]},{"raw_affiliation_string":"Gunma University Kiryu Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101691738","display_name":"Haruo Kobayashi","orcid":"https://orcid.org/0000-0002-0990-5522"},"institutions":[{"id":"https://openalex.org/I165735259","display_name":"Gunma University","ror":"https://ror.org/046fm7598","country_code":"JP","type":"education","lineage":["https://openalex.org/I165735259"]},{"id":"https://openalex.org/I258063972","display_name":"Kiryu University","ror":"https://ror.org/02snehe53","country_code":"JP","type":"education","lineage":["https://openalex.org/I258063972"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Haruo Kobayashi","raw_affiliation_strings":["Gunma University, Kiryu, Japan","Gunma University Kiryu Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Gunma University, Kiryu, Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]},{"raw_affiliation_string":"Gunma University Kiryu Japan","institution_ids":["https://openalex.org/I165735259","https://openalex.org/I258063972"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.6492,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.83555455,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"142","last_page":"143"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8940327763557434},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.7134721279144287},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6549848318099976},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6484213471412659},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6478937268257141},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5424336791038513},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5164515972137451},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5050449967384338},{"id":"https://openalex.org/keywords/uncorrelated","display_name":"Uncorrelated","score":0.49250420928001404},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4750611484050751},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.47434914112091064},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4594685733318329},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.446461945772171},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.42549729347229004},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.320284366607666},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2538384199142456},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19439005851745605},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14289575815200806}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8940327763557434},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7134721279144287},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6549848318099976},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6484213471412659},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6478937268257141},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5424336791038513},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5164515972137451},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5050449967384338},{"id":"https://openalex.org/C169345407","wikidata":"https://www.wikidata.org/wiki/Q8216221","display_name":"Uncorrelated","level":2,"score":0.49250420928001404},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4750611484050751},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.47434914112091064},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4594685733318329},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.446461945772171},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.42549729347229004},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.320284366607666},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2538384199142456},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19439005851745605},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14289575815200806},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsic.2012.6243830","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2012.6243830","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Symposium on VLSI Circuits (VLSIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W3006003651","https://openalex.org/W4386968318","https://openalex.org/W2040807843","https://openalex.org/W2088914741","https://openalex.org/W2294981364","https://openalex.org/W4247180033","https://openalex.org/W2137310043","https://openalex.org/W2337711143","https://openalex.org/W2495024767"],"abstract_inverted_index":{"A":[0],"clock":[1,16,25,31,35,66,135],"jitter":[2,44,126],"reduction":[3,123],"circuit":[4,94,140],"is":[5],"presented":[6],"that":[7,18],"exploits":[8],"the":[9,14,24,33,38,76,83,138],"phase":[10,69,104],"blending":[11,29],"technique":[12],"between":[13],"uncorrelated":[15,30,65],"edges":[17,36],"are":[19,56],"self-delayed":[20],"by":[21,48,99,136],"multiples":[22],"of":[23,51,97],"cycle,":[26],"nT.":[27,91],"By":[28],"edges,":[32,67],"output":[34],"approach":[37],"ideal":[39,77,90],"timing":[40,43,125],"and,":[41],"thus,":[42],"can":[45],"be":[46],"reduced":[47],"a":[49,114],"factor":[50],"\u221a2":[52],"per":[53],"stage.":[54],"There":[55],"three":[57],"technical":[58],"challenges":[59],"to":[60,130],"realize":[61],"this:":[62],"1)":[63],"generating":[64],"2)":[68],"averaging":[70],"with":[71,113,141],"small":[72],"time":[73],"offset":[74],"from":[75,89,127],"center":[78],"position,":[79],"and":[80,106],"3)":[81],"minimizing":[82],"error":[84],"in":[85,124,133],"nT-delay":[86,108],"being":[87],"deviated":[88],"The":[92],"proposed":[93,139],"overcomes":[95],"each":[96],"these":[98],"exploiting":[100],"an":[101,120],"nT-delay,":[102],"gated":[103],"blending,":[105],"self-calibrated":[107],"elements,":[109],"respectively.":[110],"Measurement":[111],"results":[112],"180-nm":[115],"CMOS":[116],"prototype":[117],"chip":[118],"demonstrated":[119],"approximately":[121],"fourfold":[122],"30.2":[128],"ps":[129,132],"8.8":[131],"500-MHz":[134],"cascading":[137],"four-stages.":[142]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
