{"id":"https://openalex.org/W4404954190","doi":"https://doi.org/10.1109/vlsi-soc62099.2024.10767804","title":"SystemVerilog-SystemC TestBench Architecture for VLSI Chip Design Verification","display_name":"SystemVerilog-SystemC TestBench Architecture for VLSI Chip Design Verification","publication_year":2024,"publication_date":"2024-10-06","ids":{"openalex":"https://openalex.org/W4404954190","doi":"https://doi.org/10.1109/vlsi-soc62099.2024.10767804"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc62099.2024.10767804","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc62099.2024.10767804","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070223598","display_name":"Mohammad Ismael","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Mohammad Ismael","raw_affiliation_strings":["Orion VLSI Technologies,Rawabi,Palestine§"],"affiliations":[{"raw_affiliation_string":"Orion VLSI Technologies,Rawabi,Palestine§","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022750836","display_name":"Ayman Hroub","orcid":"https://orcid.org/0009-0004-8023-6052"},"institutions":[{"id":"https://openalex.org/I94800806","display_name":"Birzeit University","ror":"https://ror.org/0256kw398","country_code":"PS","type":"education","lineage":["https://openalex.org/I94800806"]}],"countries":["PS"],"is_corresponding":false,"raw_author_name":"Ayman Hroub","raw_affiliation_strings":["Birzeit University,Department of Electrical and Computer Engineering,Birzeit,Ramallah,Palestine"],"affiliations":[{"raw_affiliation_string":"Birzeit University,Department of Electrical and Computer Engineering,Birzeit,Ramallah,Palestine","institution_ids":["https://openalex.org/I94800806"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114971709","display_name":"Nasib Naser","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nasib Naser","raw_affiliation_strings":["Orion VLSI Technologies,Rawabi,Palestine§"],"affiliations":[{"raw_affiliation_string":"Orion VLSI Technologies,Rawabi,Palestine§","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5070223598"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.23940786,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9107069969177246},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7720760107040405},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7194446325302124},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6413885951042175},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.5589842200279236},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.547778308391571},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.536983072757721},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.510033905506134},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.44292426109313965},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.332800030708313},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.18280106782913208},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.08362627029418945},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.08292099833488464}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9107069969177246},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7720760107040405},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7194446325302124},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6413885951042175},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5589842200279236},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.547778308391571},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.536983072757721},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.510033905506134},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.44292426109313965},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.332800030708313},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.18280106782913208},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.08362627029418945},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.08292099833488464},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc62099.2024.10767804","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc62099.2024.10767804","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2954722342","https://openalex.org/W3199423244","https://openalex.org/W4231857355","https://openalex.org/W4297994728"],"related_works":["https://openalex.org/W2098218272","https://openalex.org/W1581055755","https://openalex.org/W2102117846","https://openalex.org/W2132074508","https://openalex.org/W2028386630","https://openalex.org/W4256613086","https://openalex.org/W2149449165","https://openalex.org/W2547475129","https://openalex.org/W3093782403","https://openalex.org/W2362654847"],"abstract_inverted_index":{"Simulation-based":[0],"verification":[1,20,28],"of":[2,36,47,49,111],"Very-Large-Scale":[3],"Integration":[4],"(VLSI)":[5],"chip":[6],"design":[7,52],"is":[8,133],"inevitable.":[9],"However,":[10],"the":[11,19,34,45,67,80,86,92,102,107,112,125,139],"simulation":[12],"speed":[13],"can":[14,63],"be":[15,64],"a":[16],"bottleneck":[17],"in":[18,66],"process":[21],"productivity.":[22],"People":[23],"tried":[24],"to":[25,51,90,105,135],"accelerate":[26],"simulation-based":[27],"through":[29,74],"parallelization,":[30],"emulation,":[31],"and":[32,54,95],"reducing":[33],"number":[35],"test":[37],"scenarios,":[38],"etc.":[39],"In":[40],"this":[41],"paper,":[42],"we":[43],"exploited":[44],"power":[46],"abstraction":[48],"SystemC":[50,87,130],"fast":[53],"accurate":[55],"golden":[56,93],"functional":[57],"reference":[58,61,88,131,143],"models.":[59],"These":[60],"models":[62],"integrated":[65],"Universal":[68],"Verification":[69],"Methodology":[70],"(UVM)":[71],"based":[72,82,115],"TestBench":[73,83,127,140],"Transaction":[75],"Level":[76],"Modeling":[77],"(TLM).":[78],"Thus,":[79],"UVM":[81],"interacts":[84],"with":[85,129,141],"model":[89,132],"get":[91],"values,":[94],"use":[96],"them":[97],"for":[98],"checking.":[99],"We":[100],"used":[101],"proposed":[103,126],"methodology":[104],"verify":[106],"execution":[108],"unit":[109],"(EXU)":[110],"open-source":[113],"RISC-V":[114],"VeeR":[116],"EL2":[117],"processor":[118],"core.":[119],"The":[120],"experimental":[121],"results":[122],"showed":[123],"that":[124],"architecture":[128],"up":[134],"15x":[136],"faster":[137],"than":[138],"SystemVerilog":[142],"model.":[144]},"counts_by_year":[],"updated_date":"2025-12-19T19:40:27.379048","created_date":"2025-10-10T00:00:00"}