{"id":"https://openalex.org/W4404955066","doi":"https://doi.org/10.1109/vlsi-soc62099.2024.10767792","title":"Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference","display_name":"Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference","publication_year":2024,"publication_date":"2024-10-06","ids":{"openalex":"https://openalex.org/W4404955066","doi":"https://doi.org/10.1109/vlsi-soc62099.2024.10767792"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc62099.2024.10767792","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc62099.2024.10767792","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011022699","display_name":"Harideep Nair","orcid":"https://orcid.org/0009-0008-8015-4339"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Harideep Nair","raw_affiliation_strings":["Carnegie Mellon University"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021629244","display_name":"Prabhu Vellaisamy","orcid":"https://orcid.org/0009-0007-7750-8725"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prabhu Vellaisamy","raw_affiliation_strings":["Carnegie Mellon University"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101781727","display_name":"Tsung-Han Lin","orcid":"https://orcid.org/0000-0003-0149-7621"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tsung-Han Lin","raw_affiliation_strings":["MediaTek USA Inc"],"affiliations":[{"raw_affiliation_string":"MediaTek USA Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007621907","display_name":"Peiran Wang","orcid":"https://orcid.org/0009-0009-3731-1156"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Perry Wang","raw_affiliation_strings":["MediaTek USA Inc"],"affiliations":[{"raw_affiliation_string":"MediaTek USA Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039038157","display_name":"R. D. Blanton","orcid":"https://orcid.org/0000-0001-6108-2925"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shawn Blanton","raw_affiliation_strings":["Carnegie Mellon University"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102751221","display_name":"John Paul Shen","orcid":"https://orcid.org/0000-0002-7225-0629"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Paul Shen","raw_affiliation_strings":["Carnegie Mellon University"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5011022699"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19849398,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/zero","display_name":"Zero (linguistics)","score":0.5936815142631531},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5932109355926514},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.579871416091919},{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.5703549385070801},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.16211041808128357},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13731789588928223}],"concepts":[{"id":"https://openalex.org/C2780813799","wikidata":"https://www.wikidata.org/wiki/Q3274237","display_name":"Zero (linguistics)","level":2,"score":0.5936815142631531},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5932109355926514},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.579871416091919},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.5703549385070801},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.16211041808128357},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13731789588928223},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc62099.2024.10767792","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc62099.2024.10767792","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2541839172","https://openalex.org/W2931118404","https://openalex.org/W2963367920","https://openalex.org/W3037261029","https://openalex.org/W4247198796"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W4327546585","https://openalex.org/W2411923897","https://openalex.org/W4394546135","https://openalex.org/W4285347720","https://openalex.org/W4200259850","https://openalex.org/W2333831899","https://openalex.org/W2484894494"],"abstract_inverted_index":{"General":[0],"Matrix":[1],"Multiply":[2],"(GEMM)":[3],"units,":[4],"consisting":[5],"of":[6,12,30,43,79,98],"multiply-accumulate":[7],"(MAC)":[8],"arrays,":[9],"perform":[10],"bulk":[11],"the":[13,77,132,140],"computation":[14],"in":[15,83],"deep":[16],"learning":[17],"(DL).":[18],"Recent":[19],"work":[20,36],"has":[21],"proposed":[22],"a":[23,40],"novel":[24],"MAC":[25,57],"design,":[26],"Bit-Pragmatic":[27],"(PRA),":[28],"capable":[29],"dynamically":[31],"exploiting":[32],"bit":[33,81],"sparsity.":[34],"This":[35],"presents":[37],"OzMAC":[38,93],"(Omit-zero-MAC),":[39],"modified":[41],"re-implementation":[42],"PRA,":[44],"but":[45],"extends":[46],"beyond":[47],"earlier":[48],"works":[49],"by":[50,104],"performing":[51],"rigorous":[52],"post-synthesis":[53],"evaluation":[54],"against":[55],"binary":[56],"design":[58],"across":[59],"multiple":[60],"bitwidths":[61],"and":[62,89,101,107,122,150],"clock":[63,123],"frequencies":[64,124],"using":[65],"TSMC":[66],"N5":[67],"process":[68],"node":[69],"to":[70,138],"assess":[71],"commercial":[72],"implementation":[73],"potential.":[74],"We":[75],"demonstrate":[76],"existence":[78],"high":[80],"sparsity":[82],"eight":[84],"pretrained":[85],"INT8":[86],"DL":[87],"workloads":[88],"show":[90],"that":[91],"8-bit":[92,133],"improves":[94],"all":[95],"three":[96],"metrics":[97],"area,":[99],"power,":[100],"energy":[102],"significantly":[103],"21%,":[105],"70%,":[106],"28%,":[108],"respectively.":[109],"Similar":[110],"improvements":[111],"are":[112],"achieved":[113],"when":[114],"scaling":[115,135],"data":[116],"precisions":[117],"(4,":[118],"8,":[119],"16":[120],"bits)":[121],"(0.5":[125],"GHz,":[126,128],"1":[127],"1.5":[129],"GHz).":[130],"For":[131],"OzMAC,":[134],"its":[136],"frequency":[137],"normalize":[139],"throughput,":[141],"it":[142],"still":[143],"achieves":[144],"30%":[145],"improvement":[146],"on":[147],"both":[148],"power":[149],"energy.":[151]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2024-12-04T00:00:00"}