{"id":"https://openalex.org/W4308659714","doi":"https://doi.org/10.1109/vlsi-soc54400.2022.9939627","title":"Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM","display_name":"Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM","publication_year":2022,"publication_date":"2022-10-03","ids":{"openalex":"https://openalex.org/W4308659714","doi":"https://doi.org/10.1109/vlsi-soc54400.2022.9939627"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc54400.2022.9939627","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc54400.2022.9939627","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026615246","display_name":"Carlos Fern\u00e1ndez","orcid":"https://orcid.org/0000-0001-6588-9590"},"institutions":[{"id":"https://openalex.org/I75778554","display_name":"Federico Santa Mar\u00eda Technical University","ror":"https://ror.org/05510vn56","country_code":"CL","type":"education","lineage":["https://openalex.org/I75778554"]}],"countries":["CL"],"is_corresponding":true,"raw_author_name":"Carlos Fernandez","raw_affiliation_strings":["Universidad Tecnica Federico Santa Maria (UTFSM),Dept. of Electronic Engineering,Valparaiso,Chile","Dept. of Electronic Engineering, Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile"],"affiliations":[{"raw_affiliation_string":"Universidad Tecnica Federico Santa Maria (UTFSM),Dept. of Electronic Engineering,Valparaiso,Chile","institution_ids":["https://openalex.org/I75778554"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile","institution_ids":["https://openalex.org/I75778554"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030851089","display_name":"Ioannis Vourkas","orcid":"https://orcid.org/0000-0002-7036-8092"},"institutions":[{"id":"https://openalex.org/I75778554","display_name":"Federico Santa Mar\u00eda Technical University","ror":"https://ror.org/05510vn56","country_code":"CL","type":"education","lineage":["https://openalex.org/I75778554"]}],"countries":["CL"],"is_corresponding":false,"raw_author_name":"Ioannis Vourkas","raw_affiliation_strings":["Universidad Tecnica Federico Santa Maria (UTFSM),Dept. of Electronic Engineering,Valparaiso,Chile","Dept. of Electronic Engineering, Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile"],"affiliations":[{"raw_affiliation_string":"Universidad Tecnica Federico Santa Maria (UTFSM),Dept. of Electronic Engineering,Valparaiso,Chile","institution_ids":["https://openalex.org/I75778554"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile","institution_ids":["https://openalex.org/I75778554"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5026615246"],"corresponding_institution_ids":["https://openalex.org/I75778554"],"apc_list":null,"apc_paid":null,"fwci":0.2765,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.53884519,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9894999861717224,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7818776369094849},{"id":"https://openalex.org/keywords/stateful-firewall","display_name":"Stateful firewall","score":0.7407615780830383},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.5332531332969666},{"id":"https://openalex.org/keywords/in-memory-processing","display_name":"In-Memory Processing","score":0.4559413194656372},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42059725522994995},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3979372978210449},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3567313551902771},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13904744386672974},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09395396709442139},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0927824079990387},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08982613682746887}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7818776369094849},{"id":"https://openalex.org/C22927095","wikidata":"https://www.wikidata.org/wiki/Q1784206","display_name":"Stateful firewall","level":3,"score":0.7407615780830383},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.5332531332969666},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.4559413194656372},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42059725522994995},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3979372978210449},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3567313551902771},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13904744386672974},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09395396709442139},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0927824079990387},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08982613682746887},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C164120249","wikidata":"https://www.wikidata.org/wiki/Q995982","display_name":"Web search query","level":3,"score":0.0},{"id":"https://openalex.org/C194222762","wikidata":"https://www.wikidata.org/wiki/Q114486","display_name":"Query by Example","level":4,"score":0.0},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0},{"id":"https://openalex.org/C97854310","wikidata":"https://www.wikidata.org/wiki/Q19541","display_name":"Search engine","level":2,"score":0.0},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc54400.2022.9939627","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc54400.2022.9939627","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W280546096","https://openalex.org/W1982767378","https://openalex.org/W2021853834","https://openalex.org/W2066280488","https://openalex.org/W2119247813","https://openalex.org/W2195265150","https://openalex.org/W2245173025","https://openalex.org/W2516467421","https://openalex.org/W2738894409","https://openalex.org/W2768104155","https://openalex.org/W2945684349","https://openalex.org/W2953470840","https://openalex.org/W2972614379","https://openalex.org/W2996118940","https://openalex.org/W3011747191","https://openalex.org/W3024239688","https://openalex.org/W3038129536","https://openalex.org/W3089261923","https://openalex.org/W3116421392","https://openalex.org/W6677741674"],"related_works":["https://openalex.org/W3137037072","https://openalex.org/W4225907024","https://openalex.org/W4308870977","https://openalex.org/W2983750276","https://openalex.org/W3164445786","https://openalex.org/W2802367674","https://openalex.org/W2912892722","https://openalex.org/W2993390155","https://openalex.org/W2562493617","https://openalex.org/W2157007809"],"abstract_inverted_index":{"Resistive":[0],"RAM":[1],"(ReRAM)":[2],"technology":[3],"is":[4,9],"continuously":[5],"maturing":[6],"and":[7,43,59,124],"it":[8],"attracting":[10],"important":[11,138],"investments":[12],"towards":[13],"more":[14],"energy-efficient":[15],"computing":[16,22,110],"systems.":[17],"Recent":[18],"approaches":[19],"to":[20,28,74,95,105,128],"ReRAM-based":[21],"consider":[23],"the":[24,45,48,76,79,87,137],"inmemory":[25],"computations":[26,146],"equivalent":[27],"memory":[29,113,148],"read":[30,149],"operations.":[31,64,155],"In":[32],"this":[33],"context,":[34],"here":[35],"we":[36,85,116],"summarize":[37],"a":[38,51,70,100],"nonstateful":[39,91],"ratioed":[40,81,92],"logic":[41,63,82,93,97,132,145],"style":[42],"guide":[44],"reader":[46],"through":[47],"design":[49],"of":[50,69,78,90,122,130,152],"computational":[52],"1T1R":[53],"ReRAM":[54],"module":[55],"supporting":[56],"reliable,":[57],"variability-tolerant,":[58],"device":[60],"technology-independent":[61],"in-memory":[62,144],"We":[65],"present":[66],"circuit":[67],"simulations":[68],"1-bit":[71],"Full":[72],"Adder":[73],"validate":[75],"robustness":[77],"multi-level":[80],"computations.":[83],"Moreover,":[84],"underline":[86],"advantageous":[88],"performance":[89,129],"compared":[94,127],"stateful":[96,131],"alternatives.":[98],"Through":[99],"common":[101],"ground":[102],"basis":[103],"used":[104],"simplify":[106],"comparisons":[107],"by":[108,141],"translating":[109],"steps/cycles":[111],"into":[112],"read/write":[114],"operations,":[115],"found":[117],"promising":[118],"results":[119,135],"in":[120],"terms":[121],"delay":[123],"energy":[125],"consumption":[126],"counterparts.":[133],"Such":[134],"highlight":[136],"benefits":[139],"gained":[140],"basing":[142],"all":[143],"on":[147],"operations":[150],"instead":[151],"conditional":[153],"write":[154]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-10-10T00:00:00"}