{"id":"https://openalex.org/W4308575566","doi":"https://doi.org/10.1109/vlsi-soc54400.2022.9939612","title":"On the Design and Development of a ReRAM-based Computational Memory Prototype","display_name":"On the Design and Development of a ReRAM-based Computational Memory Prototype","publication_year":2022,"publication_date":"2022-10-03","ids":{"openalex":"https://openalex.org/W4308575566","doi":"https://doi.org/10.1109/vlsi-soc54400.2022.9939612"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc54400.2022.9939612","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc54400.2022.9939612","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026615246","display_name":"Carlos Fern\u00e1ndez","orcid":"https://orcid.org/0000-0001-6588-9590"},"institutions":[{"id":"https://openalex.org/I75778554","display_name":"Federico Santa Mar\u00eda Technical University","ror":"https://ror.org/05510vn56","country_code":"CL","type":"education","lineage":["https://openalex.org/I75778554"]}],"countries":["CL"],"is_corresponding":true,"raw_author_name":"Carlos Fernandez","raw_affiliation_strings":["Universidad Tecnica Federico Santa Maria (UTFSM),Dept. of Electronic Engineering,Valparaiso,Chile","Dept. of Electronic Engineering, Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile"],"affiliations":[{"raw_affiliation_string":"Universidad Tecnica Federico Santa Maria (UTFSM),Dept. of Electronic Engineering,Valparaiso,Chile","institution_ids":["https://openalex.org/I75778554"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile","institution_ids":["https://openalex.org/I75778554"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030851089","display_name":"Ioannis Vourkas","orcid":"https://orcid.org/0000-0002-7036-8092"},"institutions":[{"id":"https://openalex.org/I75778554","display_name":"Federico Santa Mar\u00eda Technical University","ror":"https://ror.org/05510vn56","country_code":"CL","type":"education","lineage":["https://openalex.org/I75778554"]}],"countries":["CL"],"is_corresponding":false,"raw_author_name":"Ioannis Vourkas","raw_affiliation_strings":["Universidad Tecnica Federico Santa Maria (UTFSM),Dept. of Electronic Engineering,Valparaiso,Chile","Dept. of Electronic Engineering, Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile"],"affiliations":[{"raw_affiliation_string":"Universidad Tecnica Federico Santa Maria (UTFSM),Dept. of Electronic Engineering,Valparaiso,Chile","institution_ids":["https://openalex.org/I75778554"]},{"raw_affiliation_string":"Dept. of Electronic Engineering, Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile","institution_ids":["https://openalex.org/I75778554"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5026615246"],"corresponding_institution_ids":["https://openalex.org/I75778554"],"apc_list":null,"apc_paid":null,"fwci":0.1829,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.48387769,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"170","issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7749693393707275},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7486494183540344},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.55215984582901},{"id":"https://openalex.org/keywords/in-memory-processing","display_name":"In-Memory Processing","score":0.5513179898262024},{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.4927990734577179},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.48034799098968506},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42610424757003784},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.37473127245903015},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3715469241142273},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.19840383529663086},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1609179675579071},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12377852201461792},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11092740297317505},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10512641072273254}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7749693393707275},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7486494183540344},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.55215984582901},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.5513179898262024},{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.4927990734577179},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.48034799098968506},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42610424757003784},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.37473127245903015},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3715469241142273},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.19840383529663086},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1609179675579071},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12377852201461792},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11092740297317505},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10512641072273254},{"id":"https://openalex.org/C164120249","wikidata":"https://www.wikidata.org/wiki/Q995982","display_name":"Web search query","level":3,"score":0.0},{"id":"https://openalex.org/C97854310","wikidata":"https://www.wikidata.org/wiki/Q19541","display_name":"Search engine","level":2,"score":0.0},{"id":"https://openalex.org/C194222762","wikidata":"https://www.wikidata.org/wiki/Q114486","display_name":"Query by Example","level":4,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc54400.2022.9939612","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc54400.2022.9939612","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2809261999","https://openalex.org/W2963385418","https://openalex.org/W3024239688","https://openalex.org/W3089261923","https://openalex.org/W4311214623","https://openalex.org/W4312729650","https://openalex.org/W6846919773"],"related_works":["https://openalex.org/W3173413269","https://openalex.org/W3137037072","https://openalex.org/W4308870977","https://openalex.org/W2983750276","https://openalex.org/W3164445786","https://openalex.org/W2802367674","https://openalex.org/W2993390155","https://openalex.org/W2912892722","https://openalex.org/W2562493617","https://openalex.org/W2157007809"],"abstract_inverted_index":{"The":[0,87,142],"use":[1],"of":[2,49,102,122,135,157,164,171],"computational":[3],"memories":[4],"based":[5,82],"on":[6,60,83,99],"ReRAM":[7,124,172],"technology":[8],"is":[9,150],"currently":[10],"being":[11],"explored":[12],"for":[13,44,109,114,176],"the":[14,45,61,65,70,107,119,123,126,147,154,162,181],"next-generation":[15],"energy-efficient":[16],"computing-in-memory":[17],"(CIM)":[18],"systems.":[19,54],"Such":[20],"approach":[21],"presents":[22],"major":[23,62],"challenges":[24],"at":[25],"device,":[26],"circuit,":[27],"and":[28,47,79,94,125],"application":[29],"level.":[30],"Thus,":[31],"this":[32,56],"MSc":[33],"Thesis":[34],"work":[35],"aims":[36],"to":[37,68,91,96,152],"establish":[38],"a":[39],"roadmap":[40,149],"towards":[41],"technologically-viable":[42],"solutions":[43],"design":[46],"development":[48,163],"industrially":[50],"appealing":[51],"ReRAM-based":[52],"CIM":[53,115,159],"To":[55],"end,":[57],"we":[58,105],"comment":[59],"steps":[63],"in":[64,140],"SW-HW":[66],"co-design":[67],"develop":[69],"memory":[71,78],"array":[72],"driving":[73],"circuitry":[74,121],"that":[75],"will":[76,131],"support":[77],"logic":[80,85,128,138],"operations":[81],"non-stateful":[84],"primitives.":[86],"latter":[88],"are":[89],"expected":[90,151],"be":[92],"variability-agnostic":[93],"not":[95],"rely":[97],"computations":[98],"probabilistic":[100],"switching":[101],"memristors.":[103],"Furthermore,":[104],"highlight":[106],"requirement":[108],"synthesis":[110],"algorithms":[111],"designed":[112],"ad-hoc":[113],"systems,":[116],"compatible":[117,168],"with":[118,169],"peripheral":[120],"underlying":[127],"primitives,":[129],"which":[130],"produce":[132],"delay/area-efficient":[133],"execution":[134],"an":[136],"arbitrary":[137],"function":[139],"memory.":[141],"complete":[143],"toolkit":[144],"resulting":[145],"from":[146],"proposed":[148],"accelerate":[153],"industrial":[155],"establishment":[156],"resistive":[158],"systems":[160],"through":[161],"functional":[165],"prototypes,":[166],"fully":[167],"imperfections":[170],"devices,":[173],"thus":[174],"useful":[175],"immediate":[177],"practical":[178],"exploitation":[179],"by":[180],"relevant":[182],"industry.":[183]},"counts_by_year":[{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}