{"id":"https://openalex.org/W3216686334","doi":"https://doi.org/10.1109/vlsi-soc53125.2021.9606998","title":"Trustworthy Hardware Design with Logic Locking","display_name":"Trustworthy Hardware Design with Logic Locking","publication_year":2021,"publication_date":"2021-10-04","ids":{"openalex":"https://openalex.org/W3216686334","doi":"https://doi.org/10.1109/vlsi-soc53125.2021.9606998","mag":"3216686334"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc53125.2021.9606998","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc53125.2021.9606998","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109485638","display_name":"Dominik \u0160i\u0161ejkovi\u0107","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dominik Sisejkovic","raw_affiliation_strings":["RWTH Aachen University, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"RWTH Aachen University, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023470562","display_name":"Rainer Leupers","orcid":"https://orcid.org/0000-0002-6735-3033"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rainer Leupers","raw_affiliation_strings":["RWTH Aachen University, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"RWTH Aachen University, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I887968799"],"apc_list":null,"apc_paid":null,"fwci":0.2234,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.40620295,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9746999740600586,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7232562303543091},{"id":"https://openalex.org/keywords/trustworthiness","display_name":"Trustworthiness","score":0.6590636372566223},{"id":"https://openalex.org/keywords/hardware-security-module","display_name":"Hardware security module","score":0.6262223720550537},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5190047025680542},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4954336881637573},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43525606393814087},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.42042621970176697},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36453741788864136},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.21094802021980286}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7232562303543091},{"id":"https://openalex.org/C153701036","wikidata":"https://www.wikidata.org/wiki/Q659974","display_name":"Trustworthiness","level":2,"score":0.6590636372566223},{"id":"https://openalex.org/C39217717","wikidata":"https://www.wikidata.org/wiki/Q1432354","display_name":"Hardware security module","level":3,"score":0.6262223720550537},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5190047025680542},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4954336881637573},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43525606393814087},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.42042621970176697},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36453741788864136},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.21094802021980286},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc53125.2021.9606998","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc53125.2021.9606998","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2771999643","https://openalex.org/W2911153941","https://openalex.org/W2945055895","https://openalex.org/W2949371427","https://openalex.org/W2968294979","https://openalex.org/W2972274212","https://openalex.org/W3023937090","https://openalex.org/W3032424280","https://openalex.org/W3041781162","https://openalex.org/W3108642877","https://openalex.org/W3162915675","https://openalex.org/W3184939553","https://openalex.org/W3186662332"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2130565894","https://openalex.org/W1944377106","https://openalex.org/W2901661247","https://openalex.org/W4312497944","https://openalex.org/W2789349722","https://openalex.org/W1984298705","https://openalex.org/W1985308002","https://openalex.org/W4247130854"],"abstract_inverted_index":{"As":[0],"the":[1,9,23,78,81,90],"designated":[2],"root":[3],"of":[4,29,80],"trust,":[5],"hardware":[6,41,61],"is":[7,28],"undoubtedly":[8],"most":[10],"critical":[11],"layer":[12],"to":[13,39],"security":[14,69],"in":[15,68],"modern":[16],"electronic":[17],"systems.":[18],"Protecting":[19],"its":[20],"integrity":[21],"throughout":[22],"integrated":[24],"circuit":[25],"supply":[26],"chain":[27],"paramount":[30],"importance.":[31],"Logic":[32],"locking":[33,57,71],"has":[34],"become":[35],"a":[36,51],"prominent":[37],"tool":[38],"safeguard":[40],"against":[42],"malicious":[43],"design":[44],"modifications.":[45],"In":[46],"this":[47],"work,":[48],"we":[49,76],"introduce":[50,65],"comprehensive":[52],"logic-locking":[53],"framework":[54,82],"that":[55],"enables":[56],"schemes":[58],"for":[59],"complex":[60],"designs.":[62],"We":[63],"further":[64],"new":[66],"concepts":[67],"metrics,":[70],"policies,":[72],"and":[73],"attacks.":[74],"Finally,":[75],"showcase":[77],"applicability":[79],"through":[83],"MiG-V\u2014the":[84],"first":[85],"logic-locked":[86],"processor":[87],"available":[88],"on":[89],"market.":[91]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}