{"id":"https://openalex.org/W2994290403","doi":"https://doi.org/10.1109/vlsi-soc.2019.8920358","title":"A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors","display_name":"A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W2994290403","doi":"https://doi.org/10.1109/vlsi-soc.2019.8920358","mag":"2994290403"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2019.8920358","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2019.8920358","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006420890","display_name":"Ganesh Gore","orcid":"https://orcid.org/0000-0002-0310-197X"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ganesh Gore","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054205742","display_name":"Patsy Cadareanu","orcid":"https://orcid.org/0000-0002-9486-5683"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patsy Cadareanu","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055536889","display_name":"Edouard Giacomin","orcid":"https://orcid.org/0000-0002-5415-1870"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Edouard Giacomin","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"172","last_page":"177"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7028482556343079},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6794869899749756},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5948197245597839},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.585541844367981},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.5589357614517212},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4872254431247711},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.48139145970344543},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4747063219547272},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.44248121976852417},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4365624487400055},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43176621198654175},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.41176673769950867},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.4109887480735779},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24518173933029175},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1875239610671997},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10702541470527649},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.095784991979599}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7028482556343079},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6794869899749756},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5948197245597839},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.585541844367981},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.5589357614517212},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4872254431247711},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.48139145970344543},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4747063219547272},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.44248121976852417},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4365624487400055},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43176621198654175},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.41176673769950867},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.4109887480735779},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24518173933029175},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1875239610671997},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10702541470527649},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.095784991979599},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2019.8920358","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2019.8920358","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1549870384","https://openalex.org/W1587386427","https://openalex.org/W1970715657","https://openalex.org/W1982177489","https://openalex.org/W2000992449","https://openalex.org/W2011829553","https://openalex.org/W2014172543","https://openalex.org/W2054095206","https://openalex.org/W2055215434","https://openalex.org/W2066949876","https://openalex.org/W2092333682","https://openalex.org/W2105808347","https://openalex.org/W2112562688","https://openalex.org/W2115795789","https://openalex.org/W2117379410","https://openalex.org/W2120000030","https://openalex.org/W2156916628","https://openalex.org/W2166127884","https://openalex.org/W2168096959","https://openalex.org/W2171608851","https://openalex.org/W2175772671","https://openalex.org/W2322754293","https://openalex.org/W2346205343","https://openalex.org/W2346682451","https://openalex.org/W2412411331","https://openalex.org/W2759368326","https://openalex.org/W2797274658","https://openalex.org/W2809707654","https://openalex.org/W2900265717","https://openalex.org/W2901679026","https://openalex.org/W2906629987","https://openalex.org/W2911566419","https://openalex.org/W2919795525","https://openalex.org/W3023413219","https://openalex.org/W3148577045","https://openalex.org/W3149318025","https://openalex.org/W3160281866","https://openalex.org/W4254569978","https://openalex.org/W6653861141"],"related_works":["https://openalex.org/W2559769120","https://openalex.org/W2617564485","https://openalex.org/W4321449671","https://openalex.org/W2897293593","https://openalex.org/W2157555699","https://openalex.org/W2187118498","https://openalex.org/W100177519","https://openalex.org/W3208050235","https://openalex.org/W2734929653","https://openalex.org/W2963778543"],"abstract_inverted_index":{"The":[0,34],"Three-Independent-Gate":[1],"Field-Effect":[2],"Transistor":[3],"(TIGFET)":[4],"is":[5,75],"a":[6,59,76,79,111,121,125,130,151,175],"promising":[7],"beyond-CMOS":[8],"technology":[9],"which":[10],"offers":[11],"many":[12],"unique":[13],"properties,":[14],"such":[15],"as":[16],"(i)":[17],"dynamic":[18],"control":[19],"of":[20,37,53,89,110,146,170],"the":[21,51,63,90,101,140,144,168],"device":[22],"polarity,":[23],"(ii)":[24],"dual":[25],"threshold":[26],"operation":[27],"and":[28,45,66,114,129,150,153,163,174],"(iii)":[29],"more":[30],"expressive":[31],"logic":[32,48,148],"capabilities.":[33],"efficient":[35],"exploitation":[36],"these":[38],"properties":[39],"provides":[40],"opportunity":[41],"to":[42],"design":[43,55,91,118,141,178],"area":[44,165],"power":[46],"optimized":[47],"circuits.":[49],"However,":[50],"evaluation":[52,88],"TIGFET-based":[54],"currently":[56],"relies":[57],"on":[58],"close":[60],"approximation":[61],"for":[62,78,100,135],"Power,":[64],"Performance,":[65],"Area":[67],"(PPA)":[68],"rather":[69],"than":[70],"traditional":[71],"layout-based":[72],"methods.":[73],"There":[74],"need":[77],"publicly":[80],"available":[81],"Process":[82],"Design":[83,122,126],"Kit":[84],"(PDK)":[85],"enabling":[86],"systematic":[87],"area.":[92],"In":[93],"this":[94],"paper,":[95],"we":[96],"propose":[97],"Predictive":[98],"PDK":[99],"10":[102],"nm-diameter":[103],"silicon-nanowire":[104],"TIGFET":[105],"device.":[106],"This":[107],"work":[108],"consists":[109],"SPICE":[112],"model":[113],"full":[115],"custom":[116],"physical":[117],"files":[119],"including":[120],"Rule":[123,127],"Manual,":[124],"Check,":[128],"Layout":[131],"Versus":[132],"Schematic":[133],"decks":[134],"Calibre\u00ae.":[136],"We":[137,160],"then":[138],"validate":[139],"rules":[142],"through":[143],"implementation":[145],"basic":[147],"gates":[149],"full-adder":[152,177],"compare":[154],"extracted":[155],"metrics":[156],"with":[157],"FreePDK15nm\u2122":[158],"PDK.":[159],"show":[161],"26%":[162],"41%":[164],"reduction":[166],"in":[167],"case":[169],"an":[171],"XOR":[172],"gate":[173],"1-bit":[176],"respectively.":[179]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":10},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":5}],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}