{"id":"https://openalex.org/W2918891770","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644996","title":"Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder","display_name":"Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2918891770","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644996","mag":"2918891770"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2018.8644996","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644996","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040668515","display_name":"Yakup Murat","orcid":null},"institutions":[{"id":"https://openalex.org/I198068145","display_name":"Scientific and Technological Research Council of Turkey","ror":"https://ror.org/04w9kkr77","country_code":"TR","type":"government","lineage":["https://openalex.org/I198068145"]}],"countries":["TR"],"is_corresponding":true,"raw_author_name":"Yakup Murat","raw_affiliation_strings":["MERT, T\u00dcB\u0130TAK \u0130LTAREN, Ankara, TURKEY"],"affiliations":[{"raw_affiliation_string":"MERT, T\u00dcB\u0130TAK \u0130LTAREN, Ankara, TURKEY","institution_ids":["https://openalex.org/I198068145"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5040668515"],"corresponding_institution_ids":["https://openalex.org/I198068145"],"apc_list":null,"apc_paid":null,"fwci":0.3187,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.64870775,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"243","last_page":"248"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.8121820688247681},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7686834335327148},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6541017293930054},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6230640411376953},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6088159680366516},{"id":"https://openalex.org/keywords/jpeg","display_name":"JPEG","score":0.5456271171569824},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5423305034637451},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5420734286308289},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.476548969745636},{"id":"https://openalex.org/keywords/lossless-compression","display_name":"Lossless compression","score":0.4749619662761688},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4728277623653412},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.43819862604141235},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40677130222320557},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4013376533985138},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2629900574684143},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.23738199472427368}],"concepts":[{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.8121820688247681},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7686834335327148},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6541017293930054},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6230640411376953},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6088159680366516},{"id":"https://openalex.org/C198751489","wikidata":"https://www.wikidata.org/wiki/Q2195","display_name":"JPEG","level":3,"score":0.5456271171569824},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5423305034637451},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5420734286308289},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.476548969745636},{"id":"https://openalex.org/C81081738","wikidata":"https://www.wikidata.org/wiki/Q55542","display_name":"Lossless compression","level":3,"score":0.4749619662761688},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4728277623653412},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.43819862604141235},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40677130222320557},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4013376533985138},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2629900574684143},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.23738199472427368},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2018.8644996","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644996","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W414960894","https://openalex.org/W1637358973","https://openalex.org/W1920091723","https://openalex.org/W2016899310","https://openalex.org/W2023400999","https://openalex.org/W2041013969","https://openalex.org/W2046775366","https://openalex.org/W2075040358","https://openalex.org/W2088079966","https://openalex.org/W2094076222","https://openalex.org/W2129111296","https://openalex.org/W2131499030","https://openalex.org/W2134554944","https://openalex.org/W2153638435","https://openalex.org/W2169405113","https://openalex.org/W2545197209","https://openalex.org/W2890089499","https://openalex.org/W6614328465","https://openalex.org/W6640084260","https://openalex.org/W6685273688","https://openalex.org/W6729306638"],"related_works":["https://openalex.org/W3106969033","https://openalex.org/W2186939576","https://openalex.org/W2357988910","https://openalex.org/W2948148442","https://openalex.org/W4322741006","https://openalex.org/W2377158164","https://openalex.org/W2187600494","https://openalex.org/W2364622490","https://openalex.org/W2013943429","https://openalex.org/W3182355142"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,8,30,33,41,75,79],"set":[4],"of":[5,11,32,58,84],"optimizations":[6,77],"for":[7,40],"efficient":[9],"implementation":[10,69],"lossless":[12],"JPEG-LS":[13,59],"encoder.":[14],"Given":[15],"approaches":[16],"are":[17,63],"not":[18],"only":[19],"based":[20],"on":[21],"digital":[22],"design":[23,56],"techniques":[24],"but":[25],"also":[26],"emerged":[27],"from":[28],"scrutinizing":[29],"regularity":[31],"algorithm.":[34],"Although":[35],"it":[36],"is":[37],"well":[38],"known":[39],"low":[42],"complexity,":[43],"former":[44],"designs":[45],"have":[46],"significant":[47],"divergences":[48],"hence":[49],"varying":[50],"performances.":[51],"In":[52],"this":[53],"context,":[54],"critical":[55],"issues":[57],"encoder":[60,73],"and":[61,87],"trade-offs":[62],"discussed":[64],"in":[65,82],"detailed":[66],"benchmark.":[67],"FPGA":[68],"results":[70],"suggest":[71],"that":[72],"with":[74],"proposed":[76],"outperforms":[78],"state-of-art":[80],"counterparts":[81],"terms":[83],"hardware":[85],"cost":[86],"throughput.":[88]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2026-03-18T14:38:29.013473","created_date":"2025-10-10T00:00:00"}