{"id":"https://openalex.org/W2918913774","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644899","title":"HLS Support for Polymorphic Parallel Memories","display_name":"HLS Support for Polymorphic Parallel Memories","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2918913774","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644899","mag":"2918913774"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2018.8644899","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085232708","display_name":"Luca Stornaiuolo","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"L. Stornaiuolo","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008834768","display_name":"Marco Rabozzi","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Rabozzi","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014181688","display_name":"Donatella Sciuto","orcid":"https://orcid.org/0000-0001-9030-6940"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"D. Sciuto","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010543929","display_name":"Marco D. Santambrogio","orcid":"https://orcid.org/0000-0002-9883-9693"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. D. Santambrogio","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074711148","display_name":"Giulio Stramondo","orcid":"https://orcid.org/0000-0002-3124-189X"},"institutions":[{"id":"https://openalex.org/I865915315","display_name":"Vrije Universiteit Amsterdam","ror":"https://ror.org/008xxew50","country_code":"NL","type":"education","lineage":["https://openalex.org/I865915315"]},{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"G. Stramondo","raw_affiliation_strings":["Universiteit van Amsterdam, Amsterdam, Netherlands"],"affiliations":[{"raw_affiliation_string":"Universiteit van Amsterdam, Amsterdam, Netherlands","institution_ids":["https://openalex.org/I865915315","https://openalex.org/I887064364"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068594581","display_name":"C\u0103t\u0103lin Bogdan Ciobanu","orcid":"https://orcid.org/0000-0002-3329-3773"},"institutions":[{"id":"https://openalex.org/I865915315","display_name":"Vrije Universiteit Amsterdam","ror":"https://ror.org/008xxew50","country_code":"NL","type":"education","lineage":["https://openalex.org/I865915315"]},{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"C. Ciobanu","raw_affiliation_strings":["Universiteit van Amsterdam, Amsterdam, Netherlands"],"affiliations":[{"raw_affiliation_string":"Universiteit van Amsterdam, Amsterdam, Netherlands","institution_ids":["https://openalex.org/I865915315","https://openalex.org/I887064364"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109847155","display_name":"Ana Lucia V\u0103rb\u0103nescu","orcid":null},"institutions":[{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]},{"id":"https://openalex.org/I865915315","display_name":"Vrije Universiteit Amsterdam","ror":"https://ror.org/008xxew50","country_code":"NL","type":"education","lineage":["https://openalex.org/I865915315"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"A. L. Varbanescu","raw_affiliation_strings":["Universiteit van Amsterdam, Amsterdam, Netherlands"],"affiliations":[{"raw_affiliation_string":"Universiteit van Amsterdam, Amsterdam, Netherlands","institution_ids":["https://openalex.org/I865915315","https://openalex.org/I887064364"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5085232708"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":0.2525,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.55169885,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"61","issue":null,"first_page":"143","last_page":"148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8461964130401611},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7469609379768372},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.7018064856529236},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5716883540153503},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.5493754744529724},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4888593554496765},{"id":"https://openalex.org/keywords/productivity","display_name":"Productivity","score":0.4785633385181427},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.46548452973365784},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.45139026641845703},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.4480321407318115},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.44012120366096497},{"id":"https://openalex.org/keywords/pci-express","display_name":"PCI Express","score":0.416363000869751},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.414841890335083},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.22793525457382202},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.08485054969787598},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08385694026947021}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8461964130401611},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7469609379768372},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.7018064856529236},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5716883540153503},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.5493754744529724},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4888593554496765},{"id":"https://openalex.org/C204983608","wikidata":"https://www.wikidata.org/wiki/Q2111958","display_name":"Productivity","level":2,"score":0.4785633385181427},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.46548452973365784},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.45139026641845703},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.4480321407318115},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.44012120366096497},{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.416363000869751},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.414841890335083},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.22793525457382202},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.08485054969787598},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08385694026947021},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsi-soc.2018.8644899","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1091639","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/1091639","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.44999998807907104,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W31398948","https://openalex.org/W2017899835","https://openalex.org/W2029779044","https://openalex.org/W2055523704","https://openalex.org/W2062647401","https://openalex.org/W2130233379","https://openalex.org/W2130416410","https://openalex.org/W2136001068","https://openalex.org/W2147282769","https://openalex.org/W2157528778","https://openalex.org/W2161118554","https://openalex.org/W2887475044","https://openalex.org/W2910891878","https://openalex.org/W6678988937","https://openalex.org/W6681787635"],"related_works":["https://openalex.org/W2995926156","https://openalex.org/W2063534976","https://openalex.org/W1604320855","https://openalex.org/W2159022270","https://openalex.org/W2102773950","https://openalex.org/W4229366200","https://openalex.org/W4281757109","https://openalex.org/W3046893044","https://openalex.org/W2168738857","https://openalex.org/W1626650477"],"abstract_inverted_index":{"The":[0],"importance":[1],"of":[2,24,61,68,99,113,126,160,167,188],"High-Level":[3],"Languages":[4],"in":[5,15,165,192],"abstracting":[6],"machine":[7],"language":[8],"to":[9,64,80],"enhance":[10],"productivity":[11,184],"has":[12,19],"been":[13],"proved":[14],"many":[16],"sectors,":[17],"and":[18,51,97,143,171],"recently":[20],"encouraged":[21],"the":[22,32,65,94,117,124,136,144,179,186],"spread":[23],"reconfigurable":[25],"hardware":[26,49,169],"for":[27,42,101,116,128],"general":[28],"purpose":[29],"computing.":[30],"At":[31],"same":[33],"time,":[34],"Field":[35],"Programmable":[36],"Gate":[37],"Arrays":[38],"(FPGAs)":[39],"become":[40],"popular":[41],"data-intensive":[43],"applications,":[44],"because":[45],"they":[46],"promise":[47],"customized":[48],"accelerators":[50],"achieve":[52],"high-performance":[53],"with":[54,139,147],"low":[55],"power":[56],"consumption.":[57],"However,":[58],"taking":[59],"advantage":[60],"parallel":[62,87],"accesses":[63],"local":[66],"memories":[67],"FPGAs":[69],"remains":[70],"difficult,":[71],"as":[72],"it":[73],"currently":[74],"requires":[75],"application":[76],"re-engineering.":[77],"A":[78],"solution":[79],"this":[81,90,105],"challenge":[82],"is":[83],"PolyMem,":[84,114],"an":[85],"easy-to-use":[86],"memory.":[88],"In":[89],"work,":[91],"we":[92,107,154],"investigate":[93],"implementation,":[95],"integration,":[96],"performance":[98],"PolyMem":[100,127,177],"HLS":[102],"applications.":[103],"To":[104],"end,":[106],"present":[108],"a":[109,140,148,156,189],"novel":[110],"open-source":[111],"implementation":[112],"optimized":[115],"Xilinx":[118],"Design":[119],"Suite.":[120],"We":[121],"further":[122],"demonstrate":[123,175],"use":[125],"three":[129,162],"different":[130],"case":[131],"studies,":[132],"implemented":[133],"using":[134],"both":[135],"Vivado":[137],"workflow":[138,146],"Virtex-7":[141],"VC707,":[142],"SDx":[145],"Kintex":[149],"Ultrascale":[150],"3":[151],"ADM-PCIE.":[152],"Finally,":[153],"provide":[155],"thorough":[157],"empirical":[158],"analysis":[159],"these":[161],"cases":[163],"studies":[164],"terms":[166],"latency,":[168],"resources,":[170],"productivity.":[172],"Our":[173],"results":[174],"that":[176],"delivers":[178],"expected":[180],"performance,":[181],"while":[182],"enhancing":[183],"at":[185],"cost":[187],"small":[190],"increase":[191],"resources.":[193]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
