{"id":"https://openalex.org/W2920148004","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644825","title":"Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor","display_name":"Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2920148004","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644825","mag":"2920148004"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2018.8644825","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644825","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021584648","display_name":"Ming Ming Wong","orcid":"https://orcid.org/0000-0002-6420-1202"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Ming Ming Wong","raw_affiliation_strings":["Hardware and Embedded Systems Lab (HESL), Nanyang Technological University (NTU), Singapore"],"affiliations":[{"raw_affiliation_string":"Hardware and Embedded Systems Lab (HESL), Nanyang Technological University (NTU), Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025451495","display_name":"Vikramkumar Pudi","orcid":"https://orcid.org/0000-0003-3992-0624"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Vikramkumar Pudi","raw_affiliation_strings":["Hardware and Embedded Systems Lab (HESL), Nanyang Technological University (NTU), Singapore"],"affiliations":[{"raw_affiliation_string":"Hardware and Embedded Systems Lab (HESL), Nanyang Technological University (NTU), Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089860351","display_name":"Anupam Chattopadhyay","orcid":"https://orcid.org/0000-0002-8818-6983"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Anupam Chattopadhyay","raw_affiliation_strings":["Hardware and Embedded Systems Lab (HESL), Nanyang Technological University (NTU), Singapore"],"affiliations":[{"raw_affiliation_string":"Hardware and Embedded Systems Lab (HESL), Nanyang Technological University (NTU), Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5021584648"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":0.8144,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.80599093,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"95","last_page":"100"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7852749824523926},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7092360854148865},{"id":"https://openalex.org/keywords/folding","display_name":"Folding (DSP implementation)","score":0.6901381015777588},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6022313237190247},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5816024541854858},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5701013803482056},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5361340641975403},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4252145290374756},{"id":"https://openalex.org/keywords/authentication","display_name":"Authentication (law)","score":0.42053431272506714},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.163213849067688},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.15400278568267822},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.1377323567867279},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09993800520896912},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08245167136192322}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7852749824523926},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7092360854148865},{"id":"https://openalex.org/C2776545253","wikidata":"https://www.wikidata.org/wiki/Q5464292","display_name":"Folding (DSP implementation)","level":2,"score":0.6901381015777588},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6022313237190247},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5816024541854858},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5701013803482056},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5361340641975403},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4252145290374756},{"id":"https://openalex.org/C148417208","wikidata":"https://www.wikidata.org/wiki/Q4825882","display_name":"Authentication (law)","level":2,"score":0.42053431272506714},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.163213849067688},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.15400278568267822},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.1377323567867279},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09993800520896912},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08245167136192322},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2018.8644825","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644825","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1545656271","https://openalex.org/W1876179543","https://openalex.org/W1972503257","https://openalex.org/W1972821547","https://openalex.org/W2010627065","https://openalex.org/W2035856475","https://openalex.org/W2059674188","https://openalex.org/W2079752511","https://openalex.org/W2107085700","https://openalex.org/W2162853544","https://openalex.org/W2556125660","https://openalex.org/W2599538801","https://openalex.org/W2745213616","https://openalex.org/W4233035441","https://openalex.org/W4255068003","https://openalex.org/W6643452263","https://openalex.org/W6735509784"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W1993041309","https://openalex.org/W4312888585","https://openalex.org/W2533938775"],"abstract_inverted_index":{"The":[0],"modern":[1],"era":[2],"of":[3,21,50,57,69,102],"Internet-of-Things":[4],"(IoT)":[5],"is":[6,53],"naturally":[7],"imposing":[8],"a":[9,71],"tight":[10],"area/runtime":[11],"constraint":[12],"on":[13,38,84,106],"the":[14,22,33,66,120,127],"computing":[15],"kernels.":[16],"Security":[17],"kernels,":[18],"as":[19,25,27],"part":[20],"standardized":[23,72],"protocols":[24],"well":[26],"custom":[28],"defense":[29],"techniques,":[30],"are":[31,91],"among":[32,126],"most":[34],"common":[35],"tasks":[36],"executed":[37],"every":[39],"digital":[40],"device.":[41],"Therefore,":[42],"low":[43],"area":[44],"cost":[45],"and":[46,77,87,96],"high":[47,97],"performance":[48,98],"implementation":[49],"security":[51,73],"kernels":[52],"an":[54],"important":[55],"goal":[56],"current":[58],"system":[59],"designers.":[60],"In":[61],"this":[62],"paper,":[63],"we":[64],"revisit":[65],"state-of-the-art":[67],"implementations":[68],"SHA-256,":[70],"primitive":[74],"for":[75],"authentication":[76],"propose":[78],"novel":[79],"optimizations.":[80],"Our":[81,114],"optimizations,":[82],"based":[83],"architectural":[85],"folding":[86],"4-2":[88],"adder":[89],"compressor,":[90],"geared":[92],"toward":[93],"both":[94],"lightweight":[95],"implementations.":[99],"Detailed":[100],"experiments":[101],"our":[103],"optimized":[104],"architecture":[105],"different":[107],"FPGA":[108],"fabrics":[109],"clearly":[110],"demonstrate":[111],"their":[112],"benefits.":[113],"presented":[115],"design":[116],"point":[117],"successfully":[118],"attained":[119],"highest":[121],"hardware":[122],"efficiency":[123],"(throughput/area)":[124],"figures":[125],"published":[128],"literature":[129],"so":[130],"far.":[131]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
