{"id":"https://openalex.org/W2919795525","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644747","title":"Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors","display_name":"Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2919795525","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644747","mag":"2919795525"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2018.8644747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644747","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055536889","display_name":"Edouard Giacomin","orcid":"https://orcid.org/0000-0002-5415-1870"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Edouard Giacomin","raw_affiliation_strings":["Electrical Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA"],"affiliations":[{"raw_affiliation_string":"Electrical Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["Electrical Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA"],"affiliations":[{"raw_affiliation_string":"Electrical Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5055536889"],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":0.9013,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.77086514,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"107","last_page":"112"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.8983361721038818},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7649185657501221},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7495769262313843},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6278157234191895},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.554163932800293},{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.5390803813934326},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.48857244849205017},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45195430517196655},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.43651413917541504},{"id":"https://openalex.org/keywords/power-semiconductor-device","display_name":"Power semiconductor device","score":0.42584842443466187},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.42376774549484253},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.26558351516723633},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2504853308200836},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.14029988646507263},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10309043526649475},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1000402569770813}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.8983361721038818},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7649185657501221},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7495769262313843},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6278157234191895},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.554163932800293},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.5390803813934326},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.48857244849205017},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45195430517196655},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.43651413917541504},{"id":"https://openalex.org/C129014197","wikidata":"https://www.wikidata.org/wiki/Q906544","display_name":"Power semiconductor device","level":3,"score":0.42584842443466187},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.42376774549484253},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.26558351516723633},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2504853308200836},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.14029988646507263},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10309043526649475},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1000402569770813},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2018.8644747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644747","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320310260","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1548656471","https://openalex.org/W1549320745","https://openalex.org/W1549962104","https://openalex.org/W1550842947","https://openalex.org/W1594464909","https://openalex.org/W1602420333","https://openalex.org/W1613874182","https://openalex.org/W1724890242","https://openalex.org/W1742687550","https://openalex.org/W1776822698","https://openalex.org/W1970715657","https://openalex.org/W2000992449","https://openalex.org/W2013623332","https://openalex.org/W2053832511","https://openalex.org/W2116656110","https://openalex.org/W2133707980","https://openalex.org/W2136402957","https://openalex.org/W2154909745","https://openalex.org/W2166127884","https://openalex.org/W2468019634","https://openalex.org/W2585170447","https://openalex.org/W2759368326","https://openalex.org/W2797274658","https://openalex.org/W6632896391","https://openalex.org/W6719946603"],"related_works":["https://openalex.org/W2774773774","https://openalex.org/W2765435638","https://openalex.org/W2738791420","https://openalex.org/W3017501411","https://openalex.org/W2159665945","https://openalex.org/W2917974523","https://openalex.org/W1908137878","https://openalex.org/W4252993849","https://openalex.org/W2526565644","https://openalex.org/W2759463585"],"abstract_inverted_index":{"Hardware":[0],"security":[1],"vulnerabilities":[2],"are":[3,12,34],"a":[4,61,70,86,100],"major":[5],"concern":[6],"for":[7,90,204],"embedded":[8],"computing":[9,74],"devices":[10],"which":[11],"now":[13],"used":[14],"in":[15,48,65,80,82,99,158],"many":[16],"application":[17],"such":[18,118],"as":[19,119],"credit":[20],"cards,":[21,23],"SIM":[22],"or":[24],"financial":[25],"systems,":[26],"putting":[27],"sensible":[28,55],"data":[29],"at":[30],"risk.":[31],"Such":[32],"systems":[33],"often":[35],"targeted":[36],"by":[37,188,224],"differential":[38],"power":[39,43,88,104,180,185,218],"attacks,":[40],"where":[41],"the":[42,54,111,153,168,176,179,183,205,217,222],"trace":[44,89,181,219],"can":[45,174,215],"be":[46,129],"monitored":[47],"order":[49,83],"to":[50,53,68,84,128,131,141,197,231],"get":[51],"access":[52],"data.":[56],"To":[57],"alleviate":[58],"this":[59,96,149],"issue,":[60],"possible":[62,92],"technique":[63,97,171],"proposed":[64],"literature":[66],"is":[67],"use":[69],"complementary":[71,169],"gate":[72,170],"(e.g.,":[73],"both":[75],"XOR":[76],"and":[77,103,186,192,209,221,226],"XNOR":[78],"operations":[79],"parallel)":[81],"have":[85,125],"symmetrical":[87],"all":[91],"input":[93],"combinations.":[94],"However,":[95],"results":[98],"large":[101],"area":[102],"overhead":[105],"since":[106],"it":[107],"approximatively":[108],"requires":[109],"twice":[110],"number":[112],"of":[113,155,160],"transistors.":[114],"Recently,":[115],"novel":[116],"technologies":[117],"Three-Independent-Gate":[120],"Field":[121],"Effect":[122],"Transistors":[123],"(TIGFETs)":[124],"been":[126],"shown":[127],"able":[130],"realize":[132],"compact":[133],"logic":[134],"gates":[135],"using":[136,156,167,213],"less":[137],"transistors":[138],"when":[139,195,229],"compared":[140,196,230],"Complementary":[142],"Metal":[143],"Oxide":[144],"Semiconductor":[145],"(CMOS)":[146],"technology.":[147],"In":[148,199],"paper,":[150],"we":[151,164,201],"investigate":[152],"benefits":[154],"TIGFETs":[157,173,214],"terms":[159],"hardware":[161],"security.":[162],"First,":[163],"show":[165,202],"that":[166,203],"with":[172],"reduce":[175,216],"transistor":[177,207],"count,":[178],"variation,":[182],"switching":[184,211],"leakage":[187,223],"2\u00d7,":[189],"57%,":[190],"36%":[191],"8\u00d7":[193],"respectively,":[194],"CMOS.":[198,232],"addition,":[200],"same":[206],"count":[208],"similar":[210],"power,":[212],"variation":[220],"81%":[225],"6.7\u00d7":[227],"respectively":[228]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
