{"id":"https://openalex.org/W2771654260","doi":"https://doi.org/10.1109/vlsi-soc.2017.8203492","title":"Template based synthesis for high performance computing","display_name":"Template based synthesis for high performance computing","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2771654260","doi":"https://doi.org/10.1109/vlsi-soc.2017.8203492","mag":"2771654260"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2017.8203492","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2017.8203492","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["University of Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089227518","display_name":"Yusuke Kimura","orcid":"https://orcid.org/0000-0003-2728-0017"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yusuke Kimura","raw_affiliation_strings":["University of Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052110149","display_name":"Qinhao Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Qinhao Wang","raw_affiliation_strings":["University of Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8291563987731934},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7714861035346985},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7480286955833435},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.581943154335022},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5691659450531006},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5353503823280334},{"id":"https://openalex.org/keywords/template","display_name":"Template","score":0.533950686454773},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5095934867858887},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41154545545578003},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.39786508679389954},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.389862060546875},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22063091397285461},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13050374388694763},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10660690069198608}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8291563987731934},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7714861035346985},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7480286955833435},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.581943154335022},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5691659450531006},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5353503823280334},{"id":"https://openalex.org/C82714645","wikidata":"https://www.wikidata.org/wiki/Q438331","display_name":"Template","level":2,"score":0.533950686454773},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5095934867858887},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41154545545578003},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39786508679389954},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.389862060546875},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22063091397285461},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13050374388694763},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10660690069198608},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2017.8203492","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2017.8203492","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W770402708","https://openalex.org/W1560001663","https://openalex.org/W1913226629","https://openalex.org/W1973831620","https://openalex.org/W1990832096","https://openalex.org/W2090843874","https://openalex.org/W2134734244","https://openalex.org/W2346016334","https://openalex.org/W2427843410","https://openalex.org/W2553032840","https://openalex.org/W2616644463","https://openalex.org/W6622411341"],"related_works":["https://openalex.org/W2121300814","https://openalex.org/W4234406076","https://openalex.org/W1886613375","https://openalex.org/W4236081792","https://openalex.org/W4250583430","https://openalex.org/W2612099726","https://openalex.org/W2160632767","https://openalex.org/W4313484792","https://openalex.org/W2121053958","https://openalex.org/W4282568311"],"abstract_inverted_index":{"Although":[0],"FPGA":[1,86],"based":[2,55,65],"implementation":[3,19,87],"of":[4,111],"software":[5,25],"can":[6,26],"give":[7],"us":[8],"not":[9,35],"only":[10],"higher":[11],"performance":[12,50,84],"but":[13],"also":[14],"energy":[15],"efficient":[16,18],"computing,":[17],"algorithms":[20],"as":[21,24,40],"hardware":[22,45],"and":[23],"be":[27],"significantly":[28],"different.":[29],"Typical":[30],"high-level":[31,60],"synthesis":[32,52,61,101],"methods":[33,102],"may":[34],"concentrate":[36],"on":[37,66],"this":[38,48],"issue,":[39],"they":[41],"are":[42,76,103],"targeting":[43,53],"general":[44],"designs.":[46],"In":[47],"paper":[49],"directed":[51],"throughput":[54],"computations":[56],"rather":[57],"than":[58],"traditional":[59],"techniques":[62],"is":[63],"proposed":[64,100,113],"\u201ctemplate":[67],"based\u201d":[68],"approaches.":[69],"With":[70],"templates,":[71],"given":[72],"data":[73],"flow":[74],"graphs":[75],"automatically":[77],"converted":[78],"into":[79],"the":[80,99,109,112],"ones":[81],"for":[82],"high":[83],"with":[85,98],"by":[88],"using":[89],"SAT-based":[90],"automatic":[91],"refinement":[92],"methods.":[93],"Several":[94],"experimental":[95],"case":[96],"studies":[97],"presented":[104],"in":[105],"order":[106],"to":[107],"demonstrate":[108],"usefulness":[110],"approach.":[114]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}