{"id":"https://openalex.org/W2774727266","doi":"https://doi.org/10.1109/vlsi-soc.2017.8203473","title":"Level-shifter-less approach for multi-V<inf>DD</inf> design to use body bias control in FD-SOI","display_name":"Level-shifter-less approach for multi-V<inf>DD</inf> design to use body bias control in FD-SOI","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2774727266","doi":"https://doi.org/10.1109/vlsi-soc.2017.8203473","mag":"2774727266"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2017.8203473","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2017.8203473","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030692253","display_name":"Kimiyoshi Usami","orcid":"https://orcid.org/0000-0002-8911-3313"},"institutions":[{"id":"https://openalex.org/I171481255","display_name":"Shibaura Institute of Technology","ror":"https://ror.org/020wjcq07","country_code":"JP","type":"education","lineage":["https://openalex.org/I171481255"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Kimiyoshi Usami","raw_affiliation_strings":["Graduate School of Engineering and Science, Shibaura Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering and Science, Shibaura Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I171481255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011378268","display_name":"Shunsuke Kogure","orcid":null},"institutions":[{"id":"https://openalex.org/I171481255","display_name":"Shibaura Institute of Technology","ror":"https://ror.org/020wjcq07","country_code":"JP","type":"education","lineage":["https://openalex.org/I171481255"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shunsuke Kogure","raw_affiliation_strings":["Graduate School of Engineering and Science, Shibaura Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering and Science, Shibaura Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I171481255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085021830","display_name":"Yusuke Yoshida","orcid":"https://orcid.org/0000-0002-0774-0509"},"institutions":[{"id":"https://openalex.org/I171481255","display_name":"Shibaura Institute of Technology","ror":"https://ror.org/020wjcq07","country_code":"JP","type":"education","lineage":["https://openalex.org/I171481255"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yusuke Yoshida","raw_affiliation_strings":["Graduate School of Engineering and Science, Shibaura Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering and Science, Shibaura Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I171481255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059163815","display_name":"Ryo Magasaki","orcid":null},"institutions":[{"id":"https://openalex.org/I171481255","display_name":"Shibaura Institute of Technology","ror":"https://ror.org/020wjcq07","country_code":"JP","type":"education","lineage":["https://openalex.org/I171481255"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ryo Magasaki","raw_affiliation_strings":["Graduate School of Engineering and Science, Shibaura Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering and Science, Shibaura Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I171481255"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113742339","display_name":"Hideharu Amano","orcid":null},"institutions":[{"id":"https://openalex.org/I203951103","display_name":"Keio University","ror":"https://ror.org/02kn6nx58","country_code":"JP","type":"education","lineage":["https://openalex.org/I203951103"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hideharu Amano","raw_affiliation_strings":["Department of Information and Computer science, Keio University, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Information and Computer science, Keio University, Yokohama, Japan","institution_ids":["https://openalex.org/I203951103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5030692253"],"corresponding_institution_ids":["https://openalex.org/I171481255"],"apc_list":null,"apc_paid":null,"fwci":0.2867,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.61262755,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"9","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.7211153507232666},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.6275997757911682},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.6127709150314331},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5923011302947998},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.4981040954589844},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4926462769508362},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4743551015853882},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.46667730808258057},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4463476538658142},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.43793806433677673},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42008328437805176},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.392353892326355},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3675172030925751},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3284253180027008},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.23370704054832458},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.22340452671051025},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.0762133002281189}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.7211153507232666},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.6275997757911682},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6127709150314331},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5923011302947998},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.4981040954589844},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4926462769508362},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4743551015853882},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.46667730808258057},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4463476538658142},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.43793806433677673},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42008328437805176},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.392353892326355},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3675172030925751},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3284253180027008},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.23370704054832458},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.22340452671051025},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.0762133002281189},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2017.8203473","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2017.8203473","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8199999928474426,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309074","display_name":"Cadence Design Systems","ror":"https://ror.org/04w8xa018"},{"id":"https://openalex.org/F4320309545","display_name":"Synopsys","ror":"https://ror.org/013by2m91"},{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1537798744","https://openalex.org/W1997742530","https://openalex.org/W2058272898","https://openalex.org/W2101481689","https://openalex.org/W2109846948","https://openalex.org/W2118358241","https://openalex.org/W2121190917","https://openalex.org/W2134508938","https://openalex.org/W3212618473","https://openalex.org/W4211113724","https://openalex.org/W4238927715","https://openalex.org/W4238999275","https://openalex.org/W6679960821"],"related_works":["https://openalex.org/W2095795001","https://openalex.org/W1615452981","https://openalex.org/W1635260192","https://openalex.org/W1563147421","https://openalex.org/W2366050505","https://openalex.org/W2379197520","https://openalex.org/W2135901990","https://openalex.org/W1911773482","https://openalex.org/W2613131189","https://openalex.org/W4383503094"],"abstract_inverted_index":{"Level":[0],"shifters":[1],"to":[2,9,35,49],"convert":[3],"signal":[4],"swings":[5],"from":[6],"low-voltage":[7],"(VDDL)":[8],"high-voltage":[10],"(VDDH)":[11],"are":[12],"required":[13],"at":[14,86],"the":[15,37,57,78,81,99,104],"boundary":[16],"of":[17,39,65,72,92],"voltage":[18],"domains":[19],"in":[20,33,56,103],"SoC":[21],"employing":[22],"multiple":[23],"supply":[24],"voltages.":[25],"However,":[26],"they":[27],"cost":[28],"delay,":[29],"power":[30],"and":[31,60,70,88],"area":[32],"addition":[34],"increasing":[36],"complexity":[38],"physical":[40],"design.":[41],"This":[42],"paper":[43],"proposes":[44],"a":[45,51,73],"level-shifter-less":[46],"(LSL)":[47],"approach":[48,83],"use":[50],"reverse":[52],"body":[53],"bias":[54],"(RBB)":[55],"VDDH":[58,105],"domain":[59],"superior":[61],"threshold-voltage":[62],"modulation":[63],"capability":[64],"FD-SOI":[66],"devices.":[67],"Simulation":[68],"results":[69],"measurements":[71],"fabricated":[74],"chip":[75,79],"demonstrated":[76],"that":[77],"applying":[80],"LSL":[82],"correctly":[84],"operates":[85],"VDDL=0.6V":[87],"VDDH=1.2V":[89],"under":[90],"RBB":[91],"2V":[93],"for":[94],"pMOS":[95],"transistors":[96],"while":[97],"suppressing":[98],"static":[100],"dc":[101],"current":[102],"domain.":[106]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}