{"id":"https://openalex.org/W2551796596","doi":"https://doi.org/10.1109/vlsi-soc.2016.7753574","title":"A novel soft error tolerant FPGA architecture","display_name":"A novel soft error tolerant FPGA architecture","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2551796596","doi":"https://doi.org/10.1109/vlsi-soc.2016.7753574","mag":"2551796596"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2016.7753574","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2016.7753574","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012465812","display_name":"Motoki Amagasaki","orcid":"https://orcid.org/0000-0002-5196-9765"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Motoki Amagasaki","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074065085","display_name":"Yuji Nakamura","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuji Nakamura","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028871028","display_name":"Teraoka Takuya","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takuya Teraoka","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059705629","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9654-2319"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Iida","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031401749","display_name":"Toshinori Sueyoshi","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshinori Sueyoshi","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5012465812"],"corresponding_institution_ids":["https://openalex.org/I96036126"],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.59324388,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.8439052700996399},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.7728328704833984},{"id":"https://openalex.org/keywords/upset","display_name":"Upset","score":0.6803531050682068},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6667381525039673},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6423822641372681},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.6285256147384644},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.6092537641525269},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5329678058624268},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5251835584640503},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.4958289563655853},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4336596131324768},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4242808520793915},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3632819652557373},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3386687636375427},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33039334416389465},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.2610112428665161},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1582072377204895},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15687429904937744}],"concepts":[{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.8439052700996399},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.7728328704833984},{"id":"https://openalex.org/C2778002589","wikidata":"https://www.wikidata.org/wiki/Q2406791","display_name":"Upset","level":2,"score":0.6803531050682068},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6667381525039673},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6423822641372681},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.6285256147384644},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.6092537641525269},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5329678058624268},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5251835584640503},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.4958289563655853},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4336596131324768},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4242808520793915},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3632819652557373},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3386687636375427},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33039334416389465},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.2610112428665161},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1582072377204895},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15687429904937744},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2016.7753574","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2016.7753574","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1992531681","https://openalex.org/W2020872704","https://openalex.org/W2035176666","https://openalex.org/W2088559447","https://openalex.org/W2098426274","https://openalex.org/W2104886115","https://openalex.org/W2137235679","https://openalex.org/W2146543277","https://openalex.org/W2149288978","https://openalex.org/W2162713172","https://openalex.org/W2171323246","https://openalex.org/W3005986825","https://openalex.org/W4236024374","https://openalex.org/W6774046002"],"related_works":["https://openalex.org/W2102538861","https://openalex.org/W1523508240","https://openalex.org/W2622269177","https://openalex.org/W2086616086","https://openalex.org/W2978528242","https://openalex.org/W2165400042","https://openalex.org/W2160088500","https://openalex.org/W3208260600","https://openalex.org/W2012451149","https://openalex.org/W3097930358"],"abstract_inverted_index":{"Due":[0],"to":[1,13,65,88,99],"reaching":[2],"the":[3,14,59,85,108,114,119,133],"nanoscale":[4],"transistor":[5],"size,":[6],"effect":[7],"of":[8,81,110],"single":[9,24],"event":[10],"upset":[11,41],"(SEU)":[12],"memory":[15,34],"has":[16],"become":[17],"conspicuous.":[18],"In":[19,67,91],"small":[20],"device":[21],"geometries,":[22],"a":[23,33,38,79],"particle":[25],"strike":[26],"might":[27],"affect":[28],"multiple":[29,39],"adjacent":[30],"cells":[31],"in":[32,37],"array":[35],"resulting":[36],"bit":[40,101],"(MBU).":[42],"Traditional":[43],"fault":[44],"tolerance":[45],"technologies":[46],"such":[47],"as":[48],"triple":[49],"modular":[50],"redundancy":[51],"(TMR)":[52],"and":[53,62,77,84,127],"error":[54,74,96,124],"correcting":[55],"code":[56],"(ECC)":[57],"occupy":[58],"large":[60],"area":[61,109],"have":[63],"vulnerability":[64],"MBU.":[66,90],"this":[68],"research,":[69],"we":[70,93,117],"propose":[71],"DMR":[72],"based":[73,123],"correct":[75,125],"circuit":[76,83,112,126],"employ":[78],"combination":[80],"proposed":[82,111,120],"interleaving":[86,102,134],"technique":[87],"mitigate":[89],"addition,":[92],"explain":[94],"soft":[95],"simulator":[97],"developed":[98],"calculate":[100],"distance.":[103],"The":[104],"results":[105,130],"show":[106,131],"that":[107,132],"is":[113,142],"smallest":[115],"when":[116],"compare":[118],"circuit,":[121],"ECC":[122],"TMR.":[128],"Simulation":[129],"distance":[135],"which":[136],"can":[137],"conceal":[138],"all":[139],"MBU":[140],"patterns":[141],"4.":[143]},"counts_by_year":[{"year":2020,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}