{"id":"https://openalex.org/W2549611048","doi":"https://doi.org/10.1109/vlsi-soc.2016.7753568","title":"Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays","display_name":"Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2549611048","doi":"https://doi.org/10.1109/vlsi-soc.2016.7753568","mag":"2549611048"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2016.7753568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2016.7753568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074456876","display_name":"Debjyoti Bhattacharjee","orcid":"https://orcid.org/0000-0001-6561-8934"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Debjyoti Bhattacharjee","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004454650","display_name":"Farhad Merchant","orcid":"https://orcid.org/0000-0002-3708-5621"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Farhad Merchant","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089860351","display_name":"Anupam Chattopadhyay","orcid":"https://orcid.org/0000-0002-8818-6983"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Anupam Chattopadhyay","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5074456876"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":2.0214,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.88023249,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10207","display_name":"Advanced biosensing and bioanalysis techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.9525847434997559},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7756472826004028},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7706291675567627},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.5848881602287292},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5600376725196838},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5527222156524658},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4424273371696472},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33342480659484863},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32091212272644043},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.28208455443382263},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1938665807247162},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19052919745445251},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1138734519481659},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.11000356078147888},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0778031051158905}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.9525847434997559},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7756472826004028},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7706291675567627},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.5848881602287292},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5600376725196838},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5527222156524658},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4424273371696472},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33342480659484863},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32091212272644043},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.28208455443382263},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1938665807247162},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19052919745445251},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1138734519481659},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.11000356078147888},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0778031051158905},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2016.7753568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2016.7753568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1512154764","https://openalex.org/W1721195207","https://openalex.org/W1971213017","https://openalex.org/W1977492474","https://openalex.org/W1981484129","https://openalex.org/W2004107885","https://openalex.org/W2026151704","https://openalex.org/W2036687738","https://openalex.org/W2061071837","https://openalex.org/W2062013887","https://openalex.org/W2064756415","https://openalex.org/W2120742511","https://openalex.org/W2158312129","https://openalex.org/W2166098345","https://openalex.org/W2295683497","https://openalex.org/W2323986115","https://openalex.org/W2345622364","https://openalex.org/W2538818567","https://openalex.org/W2546085552","https://openalex.org/W2949748754","https://openalex.org/W6697178350","https://openalex.org/W6704402733","https://openalex.org/W7034139361"],"related_works":["https://openalex.org/W2145932742","https://openalex.org/W3005999147","https://openalex.org/W3176428941","https://openalex.org/W3089883684","https://openalex.org/W4232634182","https://openalex.org/W4301187613","https://openalex.org/W2923038022","https://openalex.org/W3008646524","https://openalex.org/W4385624997","https://openalex.org/W2593506445"],"abstract_inverted_index":{"Memristive":[0],"devices,":[1],"such":[2,61],"as":[3,26,62],"ReRAMs,":[4],"are":[5],"fast":[6],"gaining":[7],"prominence":[8],"for":[9,28,32,82,116],"their":[10],"low":[11],"leakage":[12],"power,":[13],"high":[14],"endurance":[15],"and":[16,47,70,111],"non-volatile":[17],"storage":[18],"capabilities.":[19],"ReRAM":[20],"crossbar":[21,99,106],"arrays":[22],"also":[23],"found":[24],"usage":[25],"platform":[27],"in-memory":[29],"computing,":[30],"particularly":[31],"data-intensive":[33],"computations,":[34],"due":[35],"to":[36,40],"its":[37],"inherent":[38],"capability":[39],"perform":[41],"stateful":[42],"logic":[43],"operations.":[44],"Binary":[45,90],"matrix":[46],"vector":[48,118],"operations":[49,115],"arise":[50],"in":[51,71],"several":[52],"applications":[53],"that":[54],"require":[55],"close":[56],"interaction":[57],"with":[58],"the":[59,83,103,109],"storage,":[60],"Error":[63],"Correction":[64],"Codes":[65],"(ECC),":[66],"approximate":[67],"graph":[68],"mining,":[69],"general,":[72],"diverse":[73],"big":[74],"data":[75],"applications.":[76],"In":[77],"this":[78],"paper,":[79],"we":[80],"explore":[81],"first":[84],"time,":[85],"an":[86],"efficient":[87],"mapping":[88],"of":[89,105,113],"Basic":[91],"Linear":[92],"Algebra":[93],"Subprograms":[94],"(BiBLAS)":[95],"onto":[96],"hybrid":[97],"CMOS-ReRAM":[98],"array.":[100],"We":[101],"investigate":[102],"impact":[104],"configurations":[107],"on":[108],"delay,":[110],"area":[112],"BiBLAS":[114],"various":[117],"sizes.":[119]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}