{"id":"https://openalex.org/W1901384934","doi":"https://doi.org/10.1109/vlsi-soc.2015.7314434","title":"Virtual prototype based on Aldebarn CPU core","display_name":"Virtual prototype based on Aldebarn CPU core","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W1901384934","doi":"https://doi.org/10.1109/vlsi-soc.2015.7314434","mag":"1901384934"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2015.7314434","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2015.7314434","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100767181","display_name":"Jae\u2010Jin Lee","orcid":"https://orcid.org/0000-0003-3260-1620"},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jae-Jin Lee","raw_affiliation_strings":["Multimedia Processor Research Team, ETRI","Multimedia Processor Research Team, ETRI, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Multimedia Processor Research Team, ETRI","institution_ids":[]},{"raw_affiliation_string":"Multimedia Processor Research Team, ETRI, South Korea","institution_ids":["https://openalex.org/I142401562"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100728732","display_name":"Chan Kim","orcid":"https://orcid.org/0000-0003-1642-6789"},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chan Kim","raw_affiliation_strings":["Multimedia Processor Research Team, ETRI","Multimedia Processor Research Team, ETRI, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Multimedia Processor Research Team, ETRI","institution_ids":[]},{"raw_affiliation_string":"Multimedia Processor Research Team, ETRI, South Korea","institution_ids":["https://openalex.org/I142401562"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077638735","display_name":"Kyungjin Byun","orcid":"https://orcid.org/0000-0002-5605-8004"},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"KyungJin Byun","raw_affiliation_strings":["Multimedia Processor Research Team, ETRI","Multimedia Processor Research Team, ETRI, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Multimedia Processor Research Team, ETRI","institution_ids":[]},{"raw_affiliation_string":"Multimedia Processor Research Team, ETRI, South Korea","institution_ids":["https://openalex.org/I142401562"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085894901","display_name":"Nak-Woong Eum","orcid":null},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"NakWoong Eum","raw_affiliation_strings":["Multimedia Processor Research Team, ETRI","Multimedia Processor Research Team, ETRI, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Multimedia Processor Research Team, ETRI","institution_ids":[]},{"raw_affiliation_string":"Multimedia Processor Research Team, ETRI, South Korea","institution_ids":["https://openalex.org/I142401562"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I142401562"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05112704,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"303","last_page":"306"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8345299363136292},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8127670288085938},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.7914838194847107},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7568903565406799},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.682744562625885},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6736340522766113},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.5319284200668335},{"id":"https://openalex.org/keywords/profiling","display_name":"Profiling (computer programming)","score":0.5120134949684143},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.5019826889038086},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.47998878359794617},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.45964670181274414},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.43723535537719727},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4263852834701538},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.42387089133262634},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1423906683921814}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8345299363136292},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8127670288085938},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.7914838194847107},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7568903565406799},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.682744562625885},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6736340522766113},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.5319284200668335},{"id":"https://openalex.org/C187191949","wikidata":"https://www.wikidata.org/wiki/Q1138496","display_name":"Profiling (computer programming)","level":2,"score":0.5120134949684143},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.5019826889038086},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.47998878359794617},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.45964670181274414},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.43723535537719727},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4263852834701538},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.42387089133262634},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1423906683921814},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2015.7314434","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2015.7314434","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1522250664","https://openalex.org/W1922932853","https://openalex.org/W1996785854","https://openalex.org/W2073944597","https://openalex.org/W6631155369"],"related_works":["https://openalex.org/W2142916228","https://openalex.org/W2393030453","https://openalex.org/W4252858011","https://openalex.org/W2167813198","https://openalex.org/W2133071611","https://openalex.org/W4238487776","https://openalex.org/W81604946","https://openalex.org/W1482369452","https://openalex.org/W4300851787","https://openalex.org/W2375820625"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,48],"virtual":[4,17],"prototype":[5,18],"based":[6],"on":[7],"the":[8],"Aldebaran":[9],"CPU":[10],"core":[11],"developed":[12],"independently":[13],"by":[14],"ETRI.":[15],"The":[16],"provides":[19],"instruction":[20],"and":[21,40],"function":[22],"profiling":[23],"functionality":[24],"for":[25,44],"software":[26],"optimization":[27],"as":[28,30],"well":[29],"standard":[31],"integration":[32],"emulation":[33],"interface":[34],"(SystemC,":[35],"Verilog,":[36],"Netlist,":[37],"etc.)":[38],"compatibility,":[39],"architecture":[41],"performance":[42],"analysis":[43],"efficient":[45],"adoption":[46],"into":[47],"system-level":[49],"design":[50],"environment.":[51]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}