{"id":"https://openalex.org/W1909298035","doi":"https://doi.org/10.1109/vlsi-soc.2015.7314432","title":"A hybrid embedded compression codec engine for ultra HD video application","display_name":"A hybrid embedded compression codec engine for ultra HD video application","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W1909298035","doi":"https://doi.org/10.1109/vlsi-soc.2015.7314432","mag":"1909298035"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2015.7314432","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2015.7314432","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051102387","display_name":"Seongmo Park","orcid":"https://orcid.org/0000-0001-8656-9094"},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seongmo Park","raw_affiliation_strings":["SoC Research Department, Multimedia Processor Research Section, Daejeon, KOREA","SoC Research Department, ETRI, Multimedia Processor Research Section, Yuseong-gu, Daejeon, KOREA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SoC Research Department, Multimedia Processor Research Section, Daejeon, KOREA","institution_ids":[]},{"raw_affiliation_string":"SoC Research Department, ETRI, Multimedia Processor Research Section, Yuseong-gu, Daejeon, KOREA","institution_ids":["https://openalex.org/I142401562"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077638735","display_name":"Kyungjin Byun","orcid":"https://orcid.org/0000-0002-5605-8004"},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyungjin Byun","raw_affiliation_strings":["SoC Research Department, Multimedia Processor Research Section, Daejeon, KOREA","SoC Research Department, ETRI, Multimedia Processor Research Section, Yuseong-gu, Daejeon, KOREA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SoC Research Department, Multimedia Processor Research Section, Daejeon, KOREA","institution_ids":[]},{"raw_affiliation_string":"SoC Research Department, ETRI, Multimedia Processor Research Section, Yuseong-gu, Daejeon, KOREA","institution_ids":["https://openalex.org/I142401562"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085894901","display_name":"Nak-Woong Eum","orcid":null},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Nak-woong Eum","raw_affiliation_strings":["SoC Research Department, Multimedia Processor Research Section, Daejeon, KOREA","SoC Research Department, ETRI, Multimedia Processor Research Section, Yuseong-gu, Daejeon, KOREA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SoC Research Department, Multimedia Processor Research Section, Daejeon, KOREA","institution_ids":[]},{"raw_affiliation_string":"SoC Research Department, ETRI, Multimedia Processor Research Section, Yuseong-gu, Daejeon, KOREA","institution_ids":["https://openalex.org/I142401562"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I142401562"],"apc_list":null,"apc_paid":null,"fwci":0.2899,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54437734,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"292","last_page":"296"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11165","display_name":"Image and Video Quality Assessment","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8405137062072754},{"id":"https://openalex.org/keywords/codec","display_name":"Codec","score":0.6752116680145264},{"id":"https://openalex.org/keywords/lossless-compression","display_name":"Lossless compression","score":0.6473816633224487},{"id":"https://openalex.org/keywords/lossy-compression","display_name":"Lossy compression","score":0.6109597682952881},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5813899040222168},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.5624513626098633},{"id":"https://openalex.org/keywords/compression-ratio","display_name":"Compression ratio","score":0.5379297137260437},{"id":"https://openalex.org/keywords/intra-frame","display_name":"Intra-frame","score":0.5265629291534424},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5110794305801392},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4328056275844574},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4142051935195923},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.409846693277359},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3402714729309082},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.2689984440803528},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2494104504585266},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.16729745268821716},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08445930480957031}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8405137062072754},{"id":"https://openalex.org/C161765866","wikidata":"https://www.wikidata.org/wiki/Q184748","display_name":"Codec","level":2,"score":0.6752116680145264},{"id":"https://openalex.org/C81081738","wikidata":"https://www.wikidata.org/wiki/Q55542","display_name":"Lossless compression","level":3,"score":0.6473816633224487},{"id":"https://openalex.org/C165021410","wikidata":"https://www.wikidata.org/wiki/Q55564","display_name":"Lossy compression","level":2,"score":0.6109597682952881},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5813899040222168},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.5624513626098633},{"id":"https://openalex.org/C25797200","wikidata":"https://www.wikidata.org/wiki/Q828137","display_name":"Compression ratio","level":3,"score":0.5379297137260437},{"id":"https://openalex.org/C125864890","wikidata":"https://www.wikidata.org/wiki/Q1262687","display_name":"Intra-frame","level":3,"score":0.5265629291534424},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5110794305801392},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4328056275844574},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4142051935195923},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.409846693277359},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3402714729309082},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.2689984440803528},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2494104504585266},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16729745268821716},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08445930480957031},{"id":"https://openalex.org/C511840579","wikidata":"https://www.wikidata.org/wiki/Q12757","display_name":"Internal combustion engine","level":2,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C171146098","wikidata":"https://www.wikidata.org/wiki/Q124192","display_name":"Automotive engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2015.7314432","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2015.7314432","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.800000011920929,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1981126830","https://openalex.org/W1993808566","https://openalex.org/W2084420179","https://openalex.org/W2096200911","https://openalex.org/W2096762208","https://openalex.org/W2103895120","https://openalex.org/W2107030587","https://openalex.org/W2126919339","https://openalex.org/W2129842670","https://openalex.org/W2131051622","https://openalex.org/W2133944400","https://openalex.org/W2134446641","https://openalex.org/W2135558537","https://openalex.org/W2168259053","https://openalex.org/W3140689851","https://openalex.org/W6671559970","https://openalex.org/W6675640499","https://openalex.org/W6675742965","https://openalex.org/W6678780150","https://openalex.org/W6680125492"],"related_works":["https://openalex.org/W1489503129","https://openalex.org/W2036077383","https://openalex.org/W2603582838","https://openalex.org/W2164932886","https://openalex.org/W1504571461","https://openalex.org/W2317601405","https://openalex.org/W2618203063","https://openalex.org/W2080140789","https://openalex.org/W2572826484","https://openalex.org/W2003802464"],"abstract_inverted_index":{"We":[0,41],"proposed":[1,68],"an":[2,36],"efficient":[3],"VLSI":[4],"hardware":[5],"architecture":[6,27,77],"of":[7,45,62,74],"the":[8,22,32,46,51,71,95],"High":[9],"Efficiency":[10],"Video":[11],"Coding":[12],"(HEVC)":[13],"using":[14,35,85],"a":[15,56,86,91],"hybrid":[16],"embedded":[17],"compression":[18,72],"algorithm":[19,69],"for":[20,50],"reducing":[21],"frame":[23],"memory":[24,33,47],"bandwidth.":[25],"This":[26],"was":[28,67,78,98],"designed":[29],"to":[30,55],"reduce":[31],"bandwidth":[34],"adaptive":[37],"prediction":[38],"lossy/lossless":[39],"algorithm.":[40,58],"saved":[42],"about":[43,99],"50%":[44],"access":[48],"cycles":[49],"reference":[52],"data":[53],"compared":[54],"previous":[57],"The":[59,76],"PSNR":[60],"degradation":[61],"0.12":[63],"dB":[64],"on":[65],"average":[66],"at":[70],"ratio":[73],"50%.":[75],"implemented":[79],"in":[80],"Verilog":[81],"HDL":[82],"and":[83],"synthesized":[84],"Synopsys":[87],"Design":[88],"Compiler":[89],"with":[90],"65nm":[92],"cell":[93],"library;":[94],"gate":[96],"count":[97],"25,000":[100],"gates.":[101]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}