{"id":"https://openalex.org/W1934350383","doi":"https://doi.org/10.1109/vlsi-soc.2015.7314387","title":"Design of asynchronous RISC CPU register-file Write-Back queue","display_name":"Design of asynchronous RISC CPU register-file Write-Back queue","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W1934350383","doi":"https://doi.org/10.1109/vlsi-soc.2015.7314387","mag":"1934350383"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2015.7314387","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2015.7314387","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":null,"any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062578406","display_name":"Matthew M. Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I82951845","display_name":"RMIT University","ror":"https://ror.org/04ttjf776","country_code":"AU","type":"education","lineage":["https://openalex.org/I82951845"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"Matthew M. Kim","raw_affiliation_strings":["Electrical & Computer Engineering, RMIT University, Melbourne, Australia","Electrical and Computer Engineering, RMIT University, Melbourne, Australia#TAB#"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, RMIT University, Melbourne, Australia","institution_ids":["https://openalex.org/I82951845"]},{"raw_affiliation_string":"Electrical and Computer Engineering, RMIT University, Melbourne, Australia#TAB#","institution_ids":["https://openalex.org/I82951845"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057674619","display_name":"Karl M. Fant","orcid":"https://orcid.org/0000-0003-0951-2136"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Karl M. Fant","raw_affiliation_strings":["Theseus Research","Theseus Research, Mountain View, CA 94040, United States"],"affiliations":[{"raw_affiliation_string":"Theseus Research","institution_ids":[]},{"raw_affiliation_string":"Theseus Research, Mountain View, CA 94040, United States","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103092491","display_name":"Paul Beckett","orcid":"https://orcid.org/0000-0001-8401-5477"},"institutions":[{"id":"https://openalex.org/I82951845","display_name":"RMIT University","ror":"https://ror.org/04ttjf776","country_code":"AU","type":"education","lineage":["https://openalex.org/I82951845"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Paul Beckett","raw_affiliation_strings":["Electrical & Computer Engineering, RMIT University, Melbourne, Australia","Electrical and Computer Engineering, RMIT University, Melbourne, Australia#TAB#"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering, RMIT University, Melbourne, Australia","institution_ids":["https://openalex.org/I82951845"]},{"raw_affiliation_string":"Electrical and Computer Engineering, RMIT University, Melbourne, Australia#TAB#","institution_ids":["https://openalex.org/I82951845"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5062578406"],"corresponding_institution_ids":["https://openalex.org/I82951845"],"apc_list":null,"apc_paid":null,"fwci":0.6597,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68982243,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8579148650169373},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.6951315402984619},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5106781125068665},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.505570650100708},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.4748808741569519},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.4663711190223694},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.44768691062927246},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4406171143054962},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.42877382040023804},{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.4209984540939331},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3941711187362671},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38248807191848755},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.1786516010761261},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15628084540367126}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8579148650169373},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.6951315402984619},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5106781125068665},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.505570650100708},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.4748808741569519},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.4663711190223694},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.44768691062927246},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4406171143054962},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.42877382040023804},{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.4209984540939331},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3941711187362671},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38248807191848755},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.1786516010761261},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15628084540367126}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/vlsi-soc.2015.7314387","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2015.7314387","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:alma.61RMIT_INST:11247901930001341","is_oa":false,"landing_page_url":"http://doi.org/10.1109/VLSI-SoC.2015.7314387","pdf_url":null,"source":{"id":"https://openalex.org/S4306402074","display_name":"RMIT Research Repository (RMIT University Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I82951845","host_organization_name":"RMIT University","host_organization_lineage":["https://openalex.org/I82951845"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"text"},{"id":"pmh:oai:figshare.com:article/27394509","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4377196282","display_name":"Figshare","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210132348","host_organization_name":"Figshare (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210132348"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:figshare.com:article/27394509","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4377196282","display_name":"Figshare","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210132348","host_organization_name":"Figshare (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210132348"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5600000023841858,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1581303739","https://openalex.org/W1582500475","https://openalex.org/W1599610804","https://openalex.org/W2009625126","https://openalex.org/W2029005287","https://openalex.org/W2066183107","https://openalex.org/W2081240624","https://openalex.org/W2100287455","https://openalex.org/W2104105510","https://openalex.org/W2106783962","https://openalex.org/W2108432348","https://openalex.org/W2121303600","https://openalex.org/W2138000055","https://openalex.org/W4231670955","https://openalex.org/W4231905827"],"related_works":["https://openalex.org/W4246807512","https://openalex.org/W3016777042","https://openalex.org/W2773075085","https://openalex.org/W3173074201","https://openalex.org/W2510306697","https://openalex.org/W2144193790","https://openalex.org/W1983778743","https://openalex.org/W2365474106","https://openalex.org/W2009783759","https://openalex.org/W4292874632"],"abstract_inverted_index":{"This":[0,67],"paper":[1],"presents":[2],"the":[3,51,54,62,75,80],"comparison":[4,68],"results":[5,69],"of":[6,11,53,64,79],"Area,":[7],"Performance":[8],"and":[9,13,58,60],"Power":[10],"FIFO":[12,59],"Data-Queue":[14,57],"on":[15],"a":[16,38,44],"logically":[17],"determined":[18],"Null":[19],"Convention":[20],"Logic":[21],"RISC":[22],"CPU":[23,81],"register":[24,30],"file":[25],"Write-Back":[26],"circuit.":[27],"A":[28],"shift":[29],"block":[31],"implemented":[32],"using":[33],"Delay-Insensitive":[34,55],"techniques":[35],"operates":[36],"in":[37],"way":[39],"that":[40],"is":[41],"identical":[42],"to":[43,74],"FIFO.":[45],"In":[46],"this":[47],"paper,":[48],"we":[49],"illustrate":[50],"architectures":[52],"Asynchronous":[56],"analyze":[61],"characteristics":[63],"these":[65],"circuits.":[66,93],"can":[70],"be":[71],"also":[72],"used":[73],"other":[76],"buffering":[77],"unit":[78],"such":[82],"as":[83],"scoreboard":[84],"for":[85],"Dynamic":[86],"scheduling":[87],"or":[88],"Cache":[89],"Controller":[90],"memory":[91],"interface":[92]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}