{"id":"https://openalex.org/W1917400885","doi":"https://doi.org/10.1109/vlsi-soc.2015.7314384","title":"Analysis and testing on delays with two time frames","display_name":"Analysis and testing on delays with two time frames","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W1917400885","doi":"https://doi.org/10.1109/vlsi-soc.2015.7314384","mag":"1917400885"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2015.7314384","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2015.7314384","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["The University of Tokyo, Tokyo, JAPAN","The University of Tokyo, JAPAN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo, Tokyo, JAPAN","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"The University of Tokyo, JAPAN","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5027837299"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"13","last_page":"18"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9860000014305115,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6505932211875916}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6505932211875916}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2015.7314384","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2015.7314384","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1465777884","https://openalex.org/W1528837436","https://openalex.org/W1549166962","https://openalex.org/W1976743403","https://openalex.org/W1985685974","https://openalex.org/W2014319462","https://openalex.org/W2041734145","https://openalex.org/W2047503989","https://openalex.org/W2097410912","https://openalex.org/W2109821587","https://openalex.org/W2118791871","https://openalex.org/W2119241964","https://openalex.org/W2146907344","https://openalex.org/W3138459719","https://openalex.org/W4235567996","https://openalex.org/W4256313551","https://openalex.org/W6628365837","https://openalex.org/W6674503701"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052","https://openalex.org/W4402327032","https://openalex.org/W2382290278"],"abstract_inverted_index":{"We":[0,35],"discuss":[1],"additional":[2,24,42,71,90],"delays":[3,25,43,91],"caused":[4,21,69],"by":[5,22,70,79,92],"various":[6],"variations":[7],"that":[8,37,201],"may":[9,188],"change":[10],"overall":[11],"\u201cobserved\u201d":[12],"behavior":[13],"of":[14,29,139,147,159,167,181,209,216,228],"circuits.":[15],"First":[16],"we":[17,54,150,187],"analyze":[18,121],"functional":[19,57,219],"changes":[20],"such":[23,41,66],"on":[26,50,133,156],"the":[27,33,83,87,144,148,168,217],"inputs":[28],"each":[30],"gate":[31],"in":[32,86,99,143,225],"circuit.":[34],"show":[36],"unlike":[38],"stuck-at":[39],"faults,":[40],"can":[44,76,104],"introduce":[45],"many":[46,107],"more":[47],"faulty":[48],"functions":[49],"a":[51,56,226],"gate,":[52],"and":[53,94],"propose":[55],"delay":[58,220],"fault":[59,74,109,134,140,160,221],"model":[60,75],"with":[61,123,136],"two":[62],"time":[63],"frames":[64],"for":[65,171,203,212],"changed":[67],"behaviors":[68],"delays.":[72],"The":[73],"be":[77,105,112,190],"examined":[78],"tester":[80],"equipments":[81],"utilizing":[82],"scan":[84],"paths":[85],"chips.":[88],"As":[89,173],"variation":[93],"other":[95],"reasons":[96],"naturally":[97],"happen":[98],"multiple":[100,108,214],"locations":[101],"simultaneously,":[102],"there":[103],"exponentially":[106,185],"combinations":[110,215],"to":[111,120,192],"considered.":[113],"It":[114],"is":[115,163],"not":[116],"at":[117],"all":[118,213],"easy":[119],"it":[122],"traditional":[124],"automatic":[125],"test":[126,210],"pattern":[127],"generation":[128],"(ATPG)":[129],"methods":[130],"which":[131,162],"rely":[132],"dropping":[135],"explicit":[137],"representation":[138,158],"lists.":[141],"So":[142],"second":[145],"part":[146,166],"paper,":[149],"present":[151],"an":[152],"ATPG":[153,195],"method":[154],"based":[155],"implicit":[157],"lists":[161],"formulated":[164],"as":[165],"SAT":[169],"problem":[170],"ATPG.":[172],"faults":[174,183],"are":[175,184,222],"represented":[176],"implicitly,":[177],"even":[178,202],"if":[179],"numbers":[180],"simultaneous":[182],"large,":[186],"still":[189],"able":[191],"successfully":[193,223],"perform":[194],"processes.":[196],"Experimental":[197],"results":[198],"have":[199],"shown":[200],"ISCAS89":[204],"large":[205],"circuits,":[206],"complete":[207],"sets":[208],"vectors":[211],"proposed":[218],"generated":[224],"couple":[227],"hours":[229],"or":[230],"so.":[231]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
