{"id":"https://openalex.org/W2542332651","doi":"https://doi.org/10.1109/vlsi-soc.2014.7004186","title":"Improved read and write margins using a novel 8T-SRAM cell","display_name":"Improved read and write margins using a novel 8T-SRAM cell","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W2542332651","doi":"https://doi.org/10.1109/vlsi-soc.2014.7004186","mag":"2542332651"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2014.7004186","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2014.7004186","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043716992","display_name":"Farshad Moradi","orcid":"https://orcid.org/0000-0001-7077-8545"},"institutions":[{"id":"https://openalex.org/I204337017","display_name":"Aarhus University","ror":"https://ror.org/01aj84f44","country_code":"DK","type":"education","lineage":["https://openalex.org/I204337017"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Farshad Moradi","raw_affiliation_strings":["Department of Engineering, Aarhus University, Aarhus, Denmark"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Engineering, Aarhus University, Aarhus, Denmark","institution_ids":["https://openalex.org/I204337017"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100862700","display_name":"Jens Kargaard Madsen","orcid":null},"institutions":[{"id":"https://openalex.org/I204337017","display_name":"Aarhus University","ror":"https://ror.org/01aj84f44","country_code":"DK","type":"education","lineage":["https://openalex.org/I204337017"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Jens K. Madsen","raw_affiliation_strings":["Department of Engineering, Aarhus University, Aarhus, Denmark"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Engineering, Aarhus University, Aarhus, Denmark","institution_ids":["https://openalex.org/I204337017"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I204337017"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9272798895835876},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6265270709991455},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5552887320518494},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5105918049812317},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5001876354217529},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.48509109020233154},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4819600284099579},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.4776821732521057},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.4560709595680237},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.4482033848762512},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.4275423586368561},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.29152125120162964},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2581818103790283},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24424082040786743},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23563051223754883},{"id":"https://openalex.org/keywords/chemistry","display_name":"Chemistry","score":0.05945467948913574}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9272798895835876},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6265270709991455},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5552887320518494},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5105918049812317},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5001876354217529},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.48509109020233154},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4819600284099579},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.4776821732521057},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.4560709595680237},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.4482033848762512},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.4275423586368561},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29152125120162964},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2581818103790283},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24424082040786743},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23563051223754883},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.05945467948913574},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsi-soc.2014.7004186","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2014.7004186","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:publications/4caadf12-4c37-4275-aa67-ec66d8a8c442","is_oa":false,"landing_page_url":"https://pure.au.dk/portal/en/publications/4caadf12-4c37-4275-aa67-ec66d8a8c442","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Moradi, F & Madsen, J K 2014, Improved read and write margins using a novel 8T-SRAM cell. in L Garcia (ed.), 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) : Conference Proceedings. IEEE, pp. 1-5, IFIP/IEEE International Conference on Very Large Scale Integration , Playa del Carmen, Mexico, 06/10/2014. https://doi.org/10.1109/VLSI-SoC.2014.7004186","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8199999928474426}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1977413415","https://openalex.org/W2002612140","https://openalex.org/W2012031251","https://openalex.org/W2031020852","https://openalex.org/W2062742275","https://openalex.org/W2089731760","https://openalex.org/W2094648661","https://openalex.org/W2095913060","https://openalex.org/W2106339466","https://openalex.org/W2115150948","https://openalex.org/W2123278390","https://openalex.org/W2126809390","https://openalex.org/W2136250382","https://openalex.org/W6679889208"],"related_works":["https://openalex.org/W2117824263","https://openalex.org/W2134421493","https://openalex.org/W2489257435","https://openalex.org/W2297319780","https://openalex.org/W2178217057","https://openalex.org/W1972800815","https://openalex.org/W3086682201","https://openalex.org/W2743772479","https://openalex.org/W2781976127","https://openalex.org/W2118528827"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3],"novel":[4],"subthreshold":[5],"8T-SRAM":[6],"for":[7,65],"ultra-low":[8],"power":[9,62],"applications.":[10],"The":[11,89,107],"proposed":[12,56,69,90,108],"SRAM":[13,57,91,98],"cell":[14,26,70,99],"improves":[15,93],"write":[16,94],"margin":[17,37,95],"by":[18,40,51],"at":[19,27,41,75],"least":[20,42],"22%":[21],"to":[22,45,73,102],"the":[23,46,52,55,59,68,97,103],"standard":[24,47,104],"6T-SRAM":[25,48],"supply":[28,76],"voltage":[29],"of":[30,54,96],"1V":[31],"compared.":[32],"Furthermore,":[33],"read":[34],"static":[35],"noise":[36],"is":[38,63,71,110],"improved":[39,83],"2.2X":[43],"compared":[44],"cell.":[49,106],"Although":[50],"use":[53],"cell,":[58],"total":[60],"leakage":[61,87],"increased":[64],"superthreshold":[66],"regions,":[67],"able":[72],"work":[74],"voltages":[77],"lower":[78],"than":[79],"200mV":[80],"with":[81],"significantly":[82],"robustness":[84],"without":[85],"any":[86],"increase.":[88],"design":[92],"in":[100,112],"comparison":[101],"7T-SRAM":[105],"circuit":[109],"designed":[111],"TSMC":[113],"65nm":[114],"CMOS":[115],"technology.":[116]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
