{"id":"https://openalex.org/W2542664018","doi":"https://doi.org/10.1109/vlsi-soc.2014.7004185","title":"Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability","display_name":"Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W2542664018","doi":"https://doi.org/10.1109/vlsi-soc.2014.7004185","mag":"2542664018"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2014.7004185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2014.7004185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081703172","display_name":"Moon Gi Seok","orcid":"https://orcid.org/0000-0002-8159-9910"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Moon Gi Seok","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Yuseong-gu, Daejeon, Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Yuseong-gu, Daejeon, Republic of Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052809717","display_name":"Dae Jin Park","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dae Jin Park","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Yuseong-gu, Daejeon, Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Yuseong-gu, Daejeon, Republic of Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016812143","display_name":"Geun Rae Cho","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Geun Rae Cho","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Yuseong-gu, Daejeon, Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Yuseong-gu, Daejeon, Republic of Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053501953","display_name":"Tag Gon Kim","orcid":"https://orcid.org/0000-0001-7943-6509"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]},{"id":"https://openalex.org/I4210134443","display_name":"Daejeon Institute of Science and Technology","ror":"https://ror.org/032qr1v70","country_code":"KR","type":"education","lineage":["https://openalex.org/I4210134443"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Tag Gon Kim","raw_affiliation_strings":["Korea Advanced Institute of Science and Technology, Daejeon, Daejeon, KR"],"affiliations":[{"raw_affiliation_string":"Korea Advanced Institute of Science and Technology, Daejeon, Daejeon, KR","institution_ids":["https://openalex.org/I4210134443","https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5081703172"],"corresponding_institution_ids":["https://openalex.org/I157485424"],"apc_list":null,"apc_paid":null,"fwci":1.6233,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.8646119,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11195","display_name":"Simulation Techniques and Applications","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1803","display_name":"Management Science and Operations Research"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},"topics":[{"id":"https://openalex.org/T11195","display_name":"Simulation Techniques and Applications","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1803","display_name":"Management Science and Operations Research"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.7614584565162659},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7135567665100098},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.6587400436401367},{"id":"https://openalex.org/keywords/interoperation","display_name":"Interoperation","score":0.5228707790374756},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.49872350692749023},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.43343526124954224},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.42797377705574036},{"id":"https://openalex.org/keywords/electronic-circuit-simulation","display_name":"Electronic circuit simulation","score":0.4176235496997833},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36957213282585144},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3501034379005432},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32848381996154785},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2713020443916321},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.25113531947135925},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1787819266319275},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13025128841400146},{"id":"https://openalex.org/keywords/interoperability","display_name":"Interoperability","score":0.12450158596038818},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.07902282476425171}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.7614584565162659},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7135567665100098},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.6587400436401367},{"id":"https://openalex.org/C139458680","wikidata":"https://www.wikidata.org/wiki/Q12184942","display_name":"Interoperation","level":3,"score":0.5228707790374756},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.49872350692749023},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.43343526124954224},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.42797377705574036},{"id":"https://openalex.org/C46205389","wikidata":"https://www.wikidata.org/wiki/Q1270401","display_name":"Electronic circuit simulation","level":3,"score":0.4176235496997833},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36957213282585144},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3501034379005432},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32848381996154785},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2713020443916321},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.25113531947135925},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1787819266319275},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13025128841400146},{"id":"https://openalex.org/C20136886","wikidata":"https://www.wikidata.org/wiki/Q749647","display_name":"Interoperability","level":2,"score":0.12450158596038818},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.07902282476425171},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2014.7004185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2014.7004185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323103","display_name":"Agency for Defense Development","ror":"https://ror.org/05fhe0r85"},{"id":"https://openalex.org/F4320334874","display_name":"Defense Acquisition Program Administration","ror":"https://ror.org/04bjg9m96"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W616429135","https://openalex.org/W944873468","https://openalex.org/W1522289528","https://openalex.org/W2103214683","https://openalex.org/W2104520397","https://openalex.org/W2105069495","https://openalex.org/W2106181619","https://openalex.org/W2106695788","https://openalex.org/W2109067942","https://openalex.org/W2121092270","https://openalex.org/W3142432267","https://openalex.org/W4246093543","https://openalex.org/W4248106643"],"related_works":["https://openalex.org/W54894869","https://openalex.org/W2162678295","https://openalex.org/W4238165674","https://openalex.org/W2895905110","https://openalex.org/W1544420370","https://openalex.org/W1533288443","https://openalex.org/W2129508730","https://openalex.org/W2544421437","https://openalex.org/W2384488075","https://openalex.org/W2137021519"],"abstract_inverted_index":{"Designing":[0],"a":[1,69,76,89],"mixed-signal":[2],"integrated":[3],"hardware":[4],"requires":[5],"the":[6,21,29,59,84,107,116,122,144,152,156,162,191],"mixed":[7,45],"simulation":[8,70],"for":[9,25,83],"legacy":[10,46,77],"digital":[11,26],"blocks":[12,27],"and":[13,28,42,49,64,79,99,109,161,181],"analog":[14,34],"circuits,":[15],"which":[16,171],"are":[17,54,102,165,172],"usually":[18,55],"represented":[19],"by":[20],"Verilog":[22,47,78,174],"description":[23],"language":[24],"SPICE":[30,50,61,81,86,178],"circuit":[31,51],"netlist":[32],"of":[33,111,158],"circuits.":[35],"Without":[36],"model":[37,87],"translations":[38],"or":[39,129],"source-level":[40],"modifications":[41],"to":[43,105,118,127,131,190],"simulate":[44],"models":[48],"netlists":[52],"that":[53,101],"developed":[56,166],"based":[57,93,150],"on":[58,94,151],"different":[60,140],"languages,":[62],"parameters":[63],"primitives,":[65],"this":[66],"paper":[67],"proposes":[68],"framework":[71,187],"whose":[72],"concept":[73],"is":[74],"connecting":[75],"proper":[80],"simulator":[82],"target":[85],"using":[88,134],"run-time":[90],"infrastructure":[91],"(RTI)":[92],"high":[95],"level":[96],"architecture":[97],"(HLA)":[98],"adapters":[100,164],"pluggable":[103],"libraries":[104],"enable":[106],"interoperation":[108],"integration":[110,157],"simulators":[112,160],"through":[113],"HLA.":[114],"For":[115,155],"interoperation,":[117],"exchange":[119],"analog/digital":[120,125,132],"signals,":[121],"adapter":[123,145],"converts":[124],"signals":[126,133],"events":[128,130],"user-defined,":[135],"signal-event":[136],"converters.":[137],"To":[138],"synchronize":[139],"time":[141,147],"advance":[142],"policies,":[143],"performs":[146],"synchronization":[148],"procedures":[149],"pre-simulation":[153],"concept.":[154],"Verilog/SPICE":[159],"RTI,":[163],"following":[167],"each":[168],"component":[169],"interface,":[170,176],"IEEE-std":[173,182],"procedural":[175,179],"proposed":[177,186],"interface":[180],"HLA":[183],"interface.":[184],"The":[185],"was":[188],"applied":[189],"digitally":[192],"controlled":[193],"buck":[194],"converter":[195],"simulation.":[196]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}