{"id":"https://openalex.org/W2543884671","doi":"https://doi.org/10.1109/vlsi-soc.2014.7004155","title":"Logic synthesis and verification on fixed topology","display_name":"Logic synthesis and verification on fixed topology","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W2543884671","doi":"https://doi.org/10.1109/vlsi-soc.2014.7004155","mag":"2543884671"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2014.7004155","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2014.7004155","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["University of Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["University of California, Berkeley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.8203604221343994},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6233949661254883},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5968618392944336},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5629568099975586},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5087094902992249},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47537246346473694},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.47362205386161804},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4701176881790161},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4356018602848053},{"id":"https://openalex.org/keywords/test-vector","display_name":"Test vector","score":0.41055500507354736},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37494874000549316},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3426802158355713},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.09141978621482849},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08541601896286011}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.8203604221343994},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6233949661254883},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5968618392944336},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5629568099975586},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5087094902992249},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47537246346473694},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.47362205386161804},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4701176881790161},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4356018602848053},{"id":"https://openalex.org/C100767440","wikidata":"https://www.wikidata.org/wiki/Q7705816","display_name":"Test vector","level":3,"score":0.41055500507354736},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37494874000549316},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3426802158355713},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.09141978621482849},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08541601896286011},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2014.7004155","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2014.7004155","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1503377936","https://openalex.org/W1528837436","https://openalex.org/W1549166962","https://openalex.org/W2014319462","https://openalex.org/W2042813319","https://openalex.org/W2058698066","https://openalex.org/W2118791871","https://openalex.org/W2147971753","https://openalex.org/W2149236697","https://openalex.org/W2163027960","https://openalex.org/W2170288398","https://openalex.org/W4235567996","https://openalex.org/W4246399691","https://openalex.org/W6630097642","https://openalex.org/W6631725144","https://openalex.org/W6661152573","https://openalex.org/W6665376055","https://openalex.org/W6677926612"],"related_works":["https://openalex.org/W2120257283","https://openalex.org/W2117563988","https://openalex.org/W2161696808","https://openalex.org/W4240466429","https://openalex.org/W2165817266","https://openalex.org/W1952330409","https://openalex.org/W2006457427","https://openalex.org/W2132684947","https://openalex.org/W818963952","https://openalex.org/W1493811107"],"abstract_inverted_index":{"We":[0,161],"discuss":[1],"about":[2],"logic":[3,40],"synthesis":[4,168],"and":[5,57,74,82,169],"formal":[6,148],"verification":[7,149],"of":[8,26,49,111,116,158,166],"combinational":[9],"circuits":[10,135],"mapped":[11],"to":[12,107,131],"a":[13,170],"given":[14],"fixed":[15,34,70],"topology.":[16],"Here":[17],"\u201cfixed":[18],"topology\u201d":[19],"means":[20],"that":[21,97],"circuit":[22,67],"structures":[23],"in":[24,35,54,71,105],"terms":[25],"net":[27],"lists":[28],"except":[29],"for":[30,39,125,138],"gate/cell":[31],"types":[32,48],"are":[33,46,61,129],"advance.":[36],"That":[37,144],"is,":[38,145],"synthesis,":[41],"what":[42],"should":[43],"be":[44,77,86,151],"generated":[45],"the":[47,55,59,66,90,134,167],"gates/cells":[50],"(or":[51],"simply":[52],"gates)":[53],"circuits,":[56,128],"all":[58,139],"others":[60],"prefixed":[62],"before":[63],"synthesis.":[64,113],"As":[65],"topology":[68],"is":[69],"advance,":[72],"placement":[73],"routing":[75],"could":[76],"shared":[78],"among":[79],"different":[80],"designs":[81],"minimum":[83],"ECO":[84],"can":[85,95,150],"realized":[87,152],"by":[88],"keeping":[89],"same":[91],"layout.":[92],"Also,":[93],"we":[94,98],"show":[96],"do":[99],"not":[100],"need":[101],"many":[102],"test":[103,117,123,132,159,171],"vectors":[104,124],"order":[106],"guarantee":[108],"100%":[109],"correctness":[110],"such":[112,119],"Small":[114],"numbers":[115,157],"vectors,":[118],"as":[120],"only":[121],"100":[122],"30":[126],"input":[127,141],"sufficient":[130],"if":[133],"behave":[136],"correctly":[137],"possible":[140],"value":[142],"combinations.":[143],"very":[146],"efficient":[147],"through":[153],"simulations":[154],"with":[155,175],"small":[156],"vectors.":[160],"present":[162],"SAT":[163],"based":[164],"implementation":[165],"vector":[172],"generation":[173],"method":[174],"preliminary":[176],"but":[177],"encouraging":[178],"experimental":[179],"results.":[180]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}