{"id":"https://openalex.org/W2095055041","doi":"https://doi.org/10.1109/vlsi-soc.2013.6673296","title":"Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect","display_name":"Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2095055041","doi":"https://doi.org/10.1109/vlsi-soc.2013.6673296","mag":"2095055041"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2013.6673296","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2013.6673296","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090549753","display_name":"Melvin Ifeanyichukwu Eze","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Melvin Eze","raw_affiliation_strings":["Dept. of Comp Sci and Eng., Pennsylvania State University, University Park, PA, USA","Dept. of Comp. Sci.& Eng., Pennsylvania State Univ., University Park, PA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Comp Sci and Eng., Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Dept. of Comp. Sci.& Eng., Pennsylvania State Univ., University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101738631","display_name":"\u00d6zcan \u00d6zt\u00fcrk","orcid":"https://orcid.org/0000-0002-6870-8430"},"institutions":[{"id":"https://openalex.org/I168864056","display_name":"Bilkent University","ror":"https://ror.org/02vh8a032","country_code":"TR","type":"education","lineage":["https://openalex.org/I168864056"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"Ozcan Ozturk","raw_affiliation_strings":["Dept. of Comp Eng., Bilkent University, Ankara, Turkey","Dept. of Comp Eng., Bilkent Univ., Ankara, Turkey"],"affiliations":[{"raw_affiliation_string":"Dept. of Comp Eng., Bilkent University, Ankara, Turkey","institution_ids":["https://openalex.org/I168864056"]},{"raw_affiliation_string":"Dept. of Comp Eng., Bilkent Univ., Ankara, Turkey","institution_ids":["https://openalex.org/I168864056"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101919131","display_name":"Vijaykrishnan Narayanan","orcid":"https://orcid.org/0000-0001-6266-6068"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vijaykrishnan Narayanan","raw_affiliation_strings":["Dept. of Comp Sci and Eng., Pennsylvania State University, University Park, PA, USA","Dept. of Comp. Sci.& Eng., Pennsylvania State Univ., University Park, PA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Comp Sci and Eng., Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Dept. of Comp. Sci.& Eng., Pennsylvania State Univ., University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5090549753"],"corresponding_institution_ids":["https://openalex.org/I130769515"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14407882,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"296","last_page":"301"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7335389256477356},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7018046975135803},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.580631673336029},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.5738987922668457},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.565890371799469},{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.5608993768692017},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5187202095985413},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4931933283805847},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.43429797887802124},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27468985319137573},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.2437000870704651},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1426485776901245},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12689471244812012}],"concepts":[{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7335389256477356},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7018046975135803},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.580631673336029},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.5738987922668457},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.565890371799469},{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.5608993768692017},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5187202095985413},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4931933283805847},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.43429797887802124},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27468985319137573},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.2437000870704651},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1426485776901245},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12689471244812012},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsi-soc.2013.6673296","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2013.6673296","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.bilkent.edu.tr:11693/28038","is_oa":false,"landing_page_url":"http://hdl.handle.net/11693/28038","pdf_url":null,"source":{"id":"https://openalex.org/S4306400079","display_name":"Bilkent University Institutional Repository (Bilkent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I168864056","host_organization_name":"Bilkent University","host_organization_lineage":["https://openalex.org/I168864056"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W571322228","https://openalex.org/W2043630110","https://openalex.org/W2082603453","https://openalex.org/W2103653511","https://openalex.org/W2108368155","https://openalex.org/W3147005706","https://openalex.org/W4248019697","https://openalex.org/W4251729420"],"related_works":["https://openalex.org/W2027050626","https://openalex.org/W1551902604","https://openalex.org/W4232019485","https://openalex.org/W2028052815","https://openalex.org/W2076413498","https://openalex.org/W2164834710","https://openalex.org/W1520075683","https://openalex.org/W2949851887","https://openalex.org/W2123512677","https://openalex.org/W4327499872"],"abstract_inverted_index":{"Due":[0],"to":[1,14,85],"architectural":[2],"complexity":[3],"and":[4,23,40,53,72,77,93],"process":[5],"costs,":[6],"circuit-level":[7],"solutions":[8],"are":[9],"often":[10],"the":[11,21,44,51,58,64,73],"preferred":[12],"means":[13],"resolving":[15],"signal":[16,47,69],"integrity":[17],"issues":[18],"that":[19],"affect":[20],"performance":[22],"reliability":[24],"of":[25,46,55,60,102],"on-chip":[26,38],"interconnect.":[27],"In":[28],"this":[29],"paper,":[30],"we":[31],"consider":[32],"multi-segment":[33],"bit-lines":[34],"used":[35],"in":[36,42,57,106,116],"wide":[37],"interconnect,":[39],"explore":[41],"detail":[43],"effect":[45],"transition":[48,70,88],"skew":[49,71,89],"on":[50],"delay":[52],"time":[54],"flight":[56],"presence":[59],"crosstalk.":[61],"We":[62],"present":[63],"relationship":[65],"between":[66],"segment":[67],"delay,":[68],"injected":[74],"noise":[75],"pulse":[76],"propose":[78],"a":[79],"novel":[80],"staggered":[81],"latch":[82],"bus":[83],"architecture":[84,98],"explicitly":[86],"exploit":[87],"for":[90,108],"improved":[91],"speed":[92,107],"performance.":[94],"Our":[95],"proposed":[96],"SLB":[97],"achieves":[99],"an":[100],"average":[101],"2.5X":[103],"(2.3X)":[104],"improvement":[105],"fully-aligned":[109],"(mis-aligned)":[110],"buffering":[111],"schemes":[112],"with":[113],"no":[114],"increase":[115],"area,":[117],"power":[118],"or":[119],"additional":[120],"wires":[121],"needed.":[122]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}