{"id":"https://openalex.org/W2158584428","doi":"https://doi.org/10.1109/vlsi-soc.2012.6379018","title":"On the optimized generation of Software-Based Self-Test programs for VLIW processors","display_name":"On the optimized generation of Software-Based Self-Test programs for VLIW processors","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2158584428","doi":"https://doi.org/10.1109/vlsi-soc.2012.6379018","mag":"2158584428"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2012.6379018","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2012.6379018","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073106920","display_name":"D. Sabena","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"D. Sabena","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Sonza Reorda","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021426042","display_name":"Luca Sterpone","orcid":"https://orcid.org/0000-0002-3080-2560"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Sterpone","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5073106920"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":1.4606,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.82916026,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"129","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.9136881828308105},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7400233745574951},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5503416061401367},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4721912145614624},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38656240701675415},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3663957715034485},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3551941514015198}],"concepts":[{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.9136881828308105},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7400233745574951},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5503416061401367},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4721912145614624},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38656240701675415},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3663957715034485},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3551941514015198},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vlsi-soc.2012.6379018","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2012.6379018","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:porto.polito.it:2503107","is_oa":false,"landing_page_url":"http://porto.polito.it/2503107/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1506585561","https://openalex.org/W1993582472","https://openalex.org/W1995827686","https://openalex.org/W2048395739","https://openalex.org/W2057882245","https://openalex.org/W2108286888","https://openalex.org/W2121211420","https://openalex.org/W2123715095","https://openalex.org/W2152147622","https://openalex.org/W2154237597","https://openalex.org/W2158650060","https://openalex.org/W2162696040","https://openalex.org/W2166139631","https://openalex.org/W2167273147","https://openalex.org/W2998546469","https://openalex.org/W3140566188","https://openalex.org/W3148322066","https://openalex.org/W4240141845","https://openalex.org/W6662947046"],"related_works":["https://openalex.org/W1897551170","https://openalex.org/W1991993901","https://openalex.org/W2099025818","https://openalex.org/W2004481101","https://openalex.org/W183562185","https://openalex.org/W4210998841","https://openalex.org/W1991685745","https://openalex.org/W4248970686","https://openalex.org/W2004452646","https://openalex.org/W93901327"],"abstract_inverted_index":{"Software-Based":[0],"Self-Test":[1],"(SBST)":[2],"approaches":[3],"have":[4],"shown":[5],"to":[6,11,46,76,121,128],"be":[7],"an":[8,71],"effective":[9,72],"solution":[10],"detect":[12],"permanent":[13],"faults,":[14],"both":[15],"at":[16],"the":[17,20,25,49,83,90,94,117,131,135,146,149],"end":[18],"of":[19,101,116,148],"production":[21],"process,":[22],"and":[23,93,105,134],"during":[24],"operational":[26],"phase.":[27],"However,":[28],"when":[29],"Very":[30],"Long":[31],"Instruction":[32],"Word":[33],"(VLIW)":[34],"processors":[35],"are":[36],"addressed":[37],"these":[38,53],"techniques":[39],"require":[40],"some":[41],"optimization":[42],"steps":[43],"in":[44,52],"order":[45],"properly":[47],"exploit":[48],"parallelism":[50],"intrinsic":[51],"architectures.":[54],"In":[55],"this":[56],"paper":[57],"we":[58],"present":[59],"a":[60,124,142],"new":[61],"method":[62,99,119],"that,":[63],"starting":[64],"from":[65],"previously":[66],"known":[67],"algorithms,":[68],"automatically":[69,122],"generates":[70],"test":[73,91,95,125,132],"program":[74,126],"able":[75,127],"still":[77],"reach":[78],"high":[79],"fault":[80],"coverage":[81],"on":[82,141],"VLIW":[84,110],"processor":[85,111],"under":[86],"test,":[87],"while":[88],"reducing":[89],"duration":[92],"code":[96],"size.":[97],"The":[98,113],"consists":[100],"three":[102],"parametric":[103],"phases":[104],"can":[106],"deal":[107],"with":[108],"different":[109],"models.":[112],"main":[114],"goal":[115],"proposed":[118,150],"is":[120],"obtain":[123],"effectively":[129],"reduce":[130],"time":[133],"required":[136],"resources.":[137],"Experimental":[138],"results":[139],"gathered":[140],"case":[143],"study":[144],"show":[145],"effectiveness":[147],"approach.":[151]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}