{"id":"https://openalex.org/W2151401558","doi":"https://doi.org/10.1109/vlsi-soc.2012.6379001","title":"3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory","display_name":"3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2151401558","doi":"https://doi.org/10.1109/vlsi-soc.2012.6379001","mag":"2151401558"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2012.6379001","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2012.6379001","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://infoscience.epfl.ch/bitstreams/7cdabbea-9a36-4d06-832b-8174a81b0c2e/download","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054025554","display_name":"Giulia Beanato","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Giulia Beanato","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046255006","display_name":"Igor Loi","orcid":"https://orcid.org/0000-0003-3852-4662"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Igor Loi","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072423303","display_name":"Yusuf Leblebici","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Yusuf Leblebici","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5054025554"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":0.7451,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.75929787,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"30","last_page":"35"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.780083417892456},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6017855405807495},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5312421321868896},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.521914005279541},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5138943195343018},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5021419525146484},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.49660569429397583},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.49583563208580017},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.4870741665363312},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4806984066963196},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44735774397850037},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.4267186224460602},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.41408994793891907},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.38085293769836426},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3807823359966278},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34667307138442993},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3159632980823517},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20062053203582764}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.780083417892456},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6017855405807495},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5312421321868896},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.521914005279541},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5138943195343018},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5021419525146484},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.49660569429397583},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.49583563208580017},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.4870741665363312},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4806984066963196},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44735774397850037},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.4267186224460602},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.41408994793891907},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.38085293769836426},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3807823359966278},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34667307138442993},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3159632980823517},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20062053203582764}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/vlsi-soc.2012.6379001","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2012.6379001","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.tind.io:183095","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/183095","pdf_url":"https://infoscience.epfl.ch/bitstreams/7cdabbea-9a36-4d06-832b-8174a81b0c2e/download","source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference proceedings"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.371.4717","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.371.4717","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"text"},{"id":"pmh:oai:cris.unibo.it:11585/132960","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/132960","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:infoscience.tind.io:183095","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/183095","pdf_url":"https://infoscience.epfl.ch/bitstreams/7cdabbea-9a36-4d06-832b-8174a81b0c2e/download","source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference proceedings"},"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320338370","display_name":"FP7 Information and Communication Technologies","ror":null}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2151401558.pdf","grobid_xml":"https://content.openalex.org/works/W2151401558.grobid-xml"},"referenced_works_count":16,"referenced_works":["https://openalex.org/W2011443263","https://openalex.org/W2038509324","https://openalex.org/W2047043979","https://openalex.org/W2071208935","https://openalex.org/W2086481541","https://openalex.org/W2086716781","https://openalex.org/W2101381471","https://openalex.org/W2131413854","https://openalex.org/W2132829148","https://openalex.org/W2134049183","https://openalex.org/W2153215457","https://openalex.org/W2160642395","https://openalex.org/W2162454039","https://openalex.org/W4231938743","https://openalex.org/W4234308027","https://openalex.org/W6653237175"],"related_works":["https://openalex.org/W2047684617","https://openalex.org/W4321458411","https://openalex.org/W2096506606","https://openalex.org/W2079019992","https://openalex.org/W1975698617","https://openalex.org/W4281924108","https://openalex.org/W2145484885","https://openalex.org/W1575240748","https://openalex.org/W2168550483","https://openalex.org/W2378551620"],"abstract_inverted_index":{"Abstract\u2014Shared":[0],"L1":[1,56,107],"memories":[2,108],"are":[3],"of":[4,28,37,61,120,143,162],"interest":[5],"for":[6,193],"tightlycoupled":[7],"processor":[8],"clusters":[9],"in":[10],"programmable":[11],"accelerators":[12],"as":[13],"they":[14],"provide":[15,49,103],"a":[16,29,81,133,155],"convenient":[17],"shared":[18],"memory":[19,31,44,127,138,151,156,179,200,204],"abstraction":[20],"while":[21],"avoiding":[22],"cache":[23],"coherence":[24],"overheads.":[25],"The":[26,59,90,113],"performance":[27],"shared-L1":[30],"critically":[32],"depends":[33],"on":[34,86,96,109,141,181,202],"the":[35,38,53,69,73,117,146,149,163,165,182,189,211],"architecture":[36],"low-latency":[39],"interconnect":[40,70],"between":[41,126],"processors":[42],"and":[43,72,99,129],"banks,":[45],"which":[46],"needs":[47],"to":[48,52,67,102,106,123,136,154,198],"ultra-fast":[50],"access":[51,105],"largest":[54],"possible":[55],"working":[57],"set.":[58],"advent":[60],"3D":[62,87],"technology":[63,100],"provides":[64],"new":[65],"opportunities":[66],"improve":[68],"delay":[71],"form":[74,166],"factor.":[75],"In":[76,145],"this":[77],"paper":[78],"we":[79],"propose":[80],"network":[82,91,130,190],"architecture,":[83],"3D-LIN,":[84],"based":[85,95],"integration":[88],"technology.":[89],"can":[92,168],"be":[93,169],"configured":[94,192],"user":[97],"specifications":[98],"constraints":[101],"fast":[104],"multiple":[110,137],"stacked":[111,140],"dies.":[112],"extracted":[114],"results":[115],"from":[116,132],"physical":[118],"synthesis":[119],"3D-LIN":[121],"permit":[122],"explore":[124],"trade-offs":[125],"size":[128],"latency":[131],"planar":[134,212],"design":[135],"layers":[139,180,205],"top":[142],"logic.":[144,183],"case":[147],"where":[148],"system":[150],"requirements":[152],"lead":[153],"area":[157],"that":[158],"occupies":[159],"60":[160,174],"%":[161,175,208],"chip,":[164],"factor":[167],"reduced":[170],"by":[171,176],"more":[172],"than":[173,210],"stacking":[177],"2":[178,203],"Latency":[184],"reduction":[185],"is":[186,206],"also":[187],"promising:":[188],"itself,":[191],"connecting":[194],"16":[195],"processing":[196],"elements":[197],"128":[199],"banks":[201],"24":[207],"faster":[209],"system.":[213],"I.":[214]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
