{"id":"https://openalex.org/W3090636245","doi":"https://doi.org/10.1109/vlsi-dat49148.2020.9196464","title":"Automatic Floorplanning for AI SoCs","display_name":"Automatic Floorplanning for AI SoCs","publication_year":2020,"publication_date":"2020-08-01","ids":{"openalex":"https://openalex.org/W3090636245","doi":"https://doi.org/10.1109/vlsi-dat49148.2020.9196464","mag":"3090636245"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat49148.2020.9196464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat49148.2020.9196464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002759497","display_name":"Tai\u2010Chen Chen","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Tai-Chen Chen","raw_affiliation_strings":["Maxeda Technology Inc., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Maxeda Technology Inc., Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083324971","display_name":"Pei-Yu Lee","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pei-Yu Lee","raw_affiliation_strings":["Maxeda Technology Inc., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Maxeda Technology Inc., Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089860877","display_name":"Tung-Chieh Chen","orcid":"https://orcid.org/0009-0000-3163-3634"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tung-Chieh Chen","raw_affiliation_strings":["Maxeda Technology Inc., Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Maxeda Technology Inc., Hsinchu, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5002759497"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3862,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.80821719,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7908494472503662},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7821987867355347},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.741553008556366},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6263279914855957},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5904517769813538},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5702798962593079},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.4476076662540436},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4290398955345154},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4230336546897888},{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.4118748605251312},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3661730885505676},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3582831025123596},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.271842896938324},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14038997888565063},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11629027128219604}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7908494472503662},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7821987867355347},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.741553008556366},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6263279914855957},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5904517769813538},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5702798962593079},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.4476076662540436},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4290398955345154},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4230336546897888},{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.4118748605251312},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3661730885505676},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3582831025123596},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.271842896938324},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14038997888565063},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11629027128219604},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat49148.2020.9196464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat49148.2020.9196464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2624122313","https://openalex.org/W2774125915","https://openalex.org/W2775807574","https://openalex.org/W2789724425","https://openalex.org/W2909290526","https://openalex.org/W2945592068","https://openalex.org/W3016163932","https://openalex.org/W3036696276","https://openalex.org/W4239988924","https://openalex.org/W4248769596","https://openalex.org/W4256263672","https://openalex.org/W6769808892","https://openalex.org/W6779530380"],"related_works":["https://openalex.org/W2047993371","https://openalex.org/W2462231960","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2056896932","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228"],"abstract_inverted_index":{"In":[0,31],"recent":[1],"years,":[2],"artificial":[3],"intelligence/deep":[4],"learning":[5],"field":[6],"is":[7],"growing":[8],"rapidly.":[9],"The":[10],"AI":[11,66],"system-on-chip":[12],"designs":[13,18],"are":[14],"actively":[15],"developed.":[16],"These":[17],"often":[19],"have":[20],"properties":[21],"of":[22],"many":[23],"IP":[24],"blocks/embedded":[25],"memories":[26],"and":[27,44,54,61],"complicated":[28,62],"logic":[29,63],"interconnect.":[30],"this":[32],"paper,":[33],"we":[34],"propose":[35],"an":[36],"automatic":[37],"floorplanning":[38],"algorithm":[39],"by":[40],"using":[41],"dataflow":[42],"information":[43],"design":[45],"exploration":[46],"techniques":[47],"to":[48,57],"obtain":[49],"high":[50],"quality":[51],"mixed":[52],"macro":[53],"cell":[55],"placement":[56],"handle":[58],"numerous":[59],"macros":[60],"interconnect":[64],"in":[65],"SoCs.":[67]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}