{"id":"https://openalex.org/W3091001012","doi":"https://doi.org/10.1109/vlsi-dat49148.2020.9196319","title":"Overview of the OpenROAD Digital Design Flow from RTL to GDS","display_name":"Overview of the OpenROAD Digital Design Flow from RTL to GDS","publication_year":2020,"publication_date":"2020-08-01","ids":{"openalex":"https://openalex.org/W3091001012","doi":"https://doi.org/10.1109/vlsi-dat49148.2020.9196319","mag":"3091001012"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat49148.2020.9196319","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat49148.2020.9196319","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015719218","display_name":"Sherief Reda","orcid":"https://orcid.org/0000-0001-8232-4516"},"institutions":[{"id":"https://openalex.org/I175594653","display_name":"John Brown University","ror":"https://ror.org/02ct41q97","country_code":"US","type":"education","lineage":["https://openalex.org/I175594653"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sherief Reda","raw_affiliation_strings":["Brown University"],"affiliations":[{"raw_affiliation_string":"Brown University","institution_ids":["https://openalex.org/I175594653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5015719218"],"corresponding_institution_ids":["https://openalex.org/I175594653"],"apc_list":null,"apc_paid":null,"fwci":0.6931,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.67973287,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8497254848480225},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8243332505226135},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6701136827468872},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6367061138153076},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.6069007515907288},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6001675128936768},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5993871092796326},{"id":"https://openalex.org/keywords/scripting-language","display_name":"Scripting language","score":0.5509117245674133},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.49810266494750977},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.48883718252182007},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48523831367492676},{"id":"https://openalex.org/keywords/cloud-computing","display_name":"Cloud computing","score":0.4730070233345032},{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.47108161449432373},{"id":"https://openalex.org/keywords/open-source","display_name":"Open source","score":0.465867280960083},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46223384141921997},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.41541242599487305},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.41382595896720886},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.31985995173454285},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2840202748775482},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1737767457962036}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8497254848480225},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8243332505226135},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6701136827468872},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6367061138153076},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.6069007515907288},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6001675128936768},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5993871092796326},{"id":"https://openalex.org/C61423126","wikidata":"https://www.wikidata.org/wiki/Q187432","display_name":"Scripting language","level":2,"score":0.5509117245674133},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.49810266494750977},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.48883718252182007},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48523831367492676},{"id":"https://openalex.org/C79974875","wikidata":"https://www.wikidata.org/wiki/Q483639","display_name":"Cloud computing","level":2,"score":0.4730070233345032},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.47108161449432373},{"id":"https://openalex.org/C3018397939","wikidata":"https://www.wikidata.org/wiki/Q3644502","display_name":"Open source","level":3,"score":0.465867280960083},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46223384141921997},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.41541242599487305},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.41382595896720886},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.31985995173454285},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2840202748775482},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1737767457962036},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat49148.2020.9196319","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat49148.2020.9196319","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2743305891","https://openalex.org/W2051886008","https://openalex.org/W2030503305","https://openalex.org/W1716153929","https://openalex.org/W3199828306","https://openalex.org/W3205162826","https://openalex.org/W3112090072","https://openalex.org/W2409361203","https://openalex.org/W1999810416","https://openalex.org/W4285188925"],"abstract_inverted_index":{"In":[0],"this":[1],"talk,":[2],"we":[3],"review":[4],"the":[5],"current":[6],"status":[7],"of":[8,19,50],"OpenROAD,":[9],"which":[10],"is":[11,21],"an":[12,40],"open-source":[13,36,43],"end-to-end":[14],"silicon":[15],"compiler.":[16],"The":[17,35,68,88],"goal":[18],"OpenROAD":[20],"to":[22,99],"reduce":[23],"cost,":[24],"expertise,":[25],"schedule":[26],"and":[27,46,65,73,85,96,105],"risk":[28],"barriers":[29],"that":[30,53],"face":[31],"system":[32],"designers":[33],"today.":[34],"flow":[37,69,90],"builds":[38],"around":[39],"industrial":[41],"strength":[42],"design":[44,51],"database,":[45],"incorporates":[47,71],"a":[48],"number":[49],"tools":[52,75],"include":[54],"physical":[55],"synthesis":[56],"synthesis,":[57,62],"floorplanning,":[58],"placement,":[59],"clock":[60],"tree":[61],"global":[63],"routing":[64],"detailed":[66],"routing.":[67],"also":[70],"analysis":[72],"support":[74],"for":[76],"static":[77],"timing":[78],"analysis,":[79,84],"parasitic":[80],"extraction,":[81],"power":[82],"integrity":[83],"cloud":[86],"deployment.":[87],"entire":[89],"can":[91],"be":[92],"customized":[93],"through":[94],"scripting":[95],"enables":[97],"users":[98],"experiment":[100],"with":[101],"various":[102],"tool":[103],"options":[104],"optimizations.":[106]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}