{"id":"https://openalex.org/W2950046899","doi":"https://doi.org/10.1109/vlsi-dat.2019.8741764","title":"High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks","display_name":"High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks","publication_year":2019,"publication_date":"2019-04-01","ids":{"openalex":"https://openalex.org/W2950046899","doi":"https://doi.org/10.1109/vlsi-dat.2019.8741764","mag":"2950046899"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2019.8741764","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2019.8741764","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014104140","display_name":"B. M. Prabhu Prasad","orcid":"https://orcid.org/0000-0002-6138-3012"},"institutions":[{"id":"https://openalex.org/I11880225","display_name":"National Institute of Technology Karnataka","ror":"https://ror.org/01hz4v948","country_code":"IN","type":"education","lineage":["https://openalex.org/I11880225"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"B M Prabhu Prasad","raw_affiliation_strings":["Department of Computer Science and Engineering, National Institute of Technology Karnataka, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Institute of Technology Karnataka, India","institution_ids":["https://openalex.org/I11880225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079634639","display_name":"Khyamling Parane","orcid":"https://orcid.org/0000-0003-4176-4640"},"institutions":[{"id":"https://openalex.org/I11880225","display_name":"National Institute of Technology Karnataka","ror":"https://ror.org/01hz4v948","country_code":"IN","type":"education","lineage":["https://openalex.org/I11880225"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Khyamling Parane","raw_affiliation_strings":["Department of Computer Science and Engineering, National Institute of Technology Karnataka, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Institute of Technology Karnataka, India","institution_ids":["https://openalex.org/I11880225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004440264","display_name":"Basavaraj Talawar","orcid":"https://orcid.org/0000-0001-5054-3124"},"institutions":[{"id":"https://openalex.org/I11880225","display_name":"National Institute of Technology Karnataka","ror":"https://ror.org/01hz4v948","country_code":"IN","type":"education","lineage":["https://openalex.org/I11880225"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Basavaraj Talawar","raw_affiliation_strings":["Department of Computer Science and Engineering, National Institute of Technology Karnataka, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Institute of Technology Karnataka, India","institution_ids":["https://openalex.org/I11880225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5014104140"],"corresponding_institution_ids":["https://openalex.org/I11880225"],"apc_list":null,"apc_paid":null,"fwci":0.3537,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.61866911,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.8371987342834473},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.7889745235443115},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7197353839874268},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6711105108261108},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6279487609863281},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5367451906204224},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.49088627099990845},{"id":"https://openalex.org/keywords/routing-table","display_name":"Routing table","score":0.49083858728408813},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.48698386549949646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4868592619895935},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4780176877975464},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.45749789476394653},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4365934133529663},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.42260587215423584},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.4154036343097687},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3518298268318176},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.25827616453170776},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20467093586921692},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15517419576644897},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09873524308204651},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09017056226730347}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.8371987342834473},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.7889745235443115},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7197353839874268},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6711105108261108},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6279487609863281},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5367451906204224},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.49088627099990845},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.49083858728408813},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.48698386549949646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4868592619895935},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4780176877975464},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.45749789476394653},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4365934133529663},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.42260587215423584},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.4154036343097687},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3518298268318176},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.25827616453170776},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20467093586921692},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15517419576644897},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09873524308204651},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09017056226730347},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2019.8741764","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2019.8741764","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1644436786","https://openalex.org/W1979770601","https://openalex.org/W2130183852","https://openalex.org/W2130425801","https://openalex.org/W2204870480","https://openalex.org/W2524701127","https://openalex.org/W2533190569","https://openalex.org/W2795260458","https://openalex.org/W6648697037"],"related_works":["https://openalex.org/W4323268213","https://openalex.org/W2145932742","https://openalex.org/W1972355764","https://openalex.org/W1993197222","https://openalex.org/W2576538540","https://openalex.org/W1757304091","https://openalex.org/W2152379259","https://openalex.org/W2099993311","https://openalex.org/W2226270586","https://openalex.org/W223007697"],"abstract_inverted_index":{"An":[0],"FPGA":[1,47],"based":[2,73,94,107,138],"Network":[3],"on":[4],"Chip":[5],"(NoC)":[6],"simulation":[7],"acceleration":[8],"framework":[9,157],"is":[10,25],"presented":[11],"in":[12,27,39,68,104,134],"this":[13],"paper.":[14],"The":[15,109,155],"functionality":[16],"of":[17,21,31,45,49,64,76,162],"the":[18,22,28,32,40,46,50,61,65,69,77,92,105,118,135,142,146,159,169,173],"crossbar":[19,74,95],"switch":[20],"NoC":[23,121],"router":[24],"embedded":[26],"hard":[29,62],"multiplexers":[30,63],"Xilinx":[33],"DSP48E1":[34,66],"slices.":[35],"A":[36],"significant":[37],"reduction":[38],"soft":[41],"logic":[42],"(LUT+FF)":[43],"utilization":[44],"implementation":[48,75,139],"6":[51,53,78,80],"\u00d7":[52,79],"Torus":[54,81,126,149],"topology":[55,82,127,150],"has":[56,101,131],"been":[57,102,132],"observed":[58,103],"by":[59],"employing":[60],"slices":[67],"proposed":[70,110,136,156],"work.":[71],"DSP":[72,106,137],"consumes":[83],"38%":[84],"fewer":[85,89,114],"LUTs":[86,115],"and":[87,164,172],"45%":[88],"FFs":[90],"than":[91],"LUT":[93,170],"implementation.":[96,108],"35%":[97],"less":[98],"power":[99],"consumption":[100],"work":[111],"utilizes":[112],"76%":[113],"compared":[116,140],"to":[117,141,168],"state-of-the-art":[119],"CONNECT":[120,174],"generation":[122],"tool.":[123],"Buffered,":[124],"bi-directional":[125],"with":[128,151,166],"XY":[129],"routing":[130,153],"considered":[133],"Hoplite-DSP":[143],"which":[144],"implements":[145],"bufferless,":[147],"unidirectional":[148],"deflective":[152],"algorithm.":[154],"achieves":[158],"speed":[160],"up":[161],"2.02\u00d7":[163],"2.9\u00d7":[165],"respect":[167],"only":[171],"NoCs.":[175]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}