{"id":"https://openalex.org/W2806758444","doi":"https://doi.org/10.1109/vlsi-dat.2018.8373273","title":"Triple patterning lithography-aware detailed routing ensuring via layer decomposability","display_name":"Triple patterning lithography-aware detailed routing ensuring via layer decomposability","publication_year":2018,"publication_date":"2018-04-01","ids":{"openalex":"https://openalex.org/W2806758444","doi":"https://doi.org/10.1109/vlsi-dat.2018.8373273","mag":"2806758444"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2018.8373273","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2018.8373273","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030670883","display_name":"Huayi Wu","orcid":"https://orcid.org/0000-0003-3971-0512"},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hua-Yi Wu","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065439030","display_name":"Shao\u2010Yun Fang","orcid":"https://orcid.org/0000-0001-6675-2676"},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shao-Yun Fang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5030670883"],"corresponding_institution_ids":["https://openalex.org/I154864474"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.05103525,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7065150141716003},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6925184726715088},{"id":"https://openalex.org/keywords/multiple-patterning","display_name":"Multiple patterning","score":0.5390045642852783},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4730978310108185},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.45544198155403137},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.4451674818992615},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4443266987800598},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.41281864047050476},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3262922167778015},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.298112690448761},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2896274924278259},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.26997244358062744},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.18039947748184204},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.07183703780174255}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7065150141716003},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6925184726715088},{"id":"https://openalex.org/C177409738","wikidata":"https://www.wikidata.org/wiki/Q1917460","display_name":"Multiple patterning","level":4,"score":0.5390045642852783},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4730978310108185},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.45544198155403137},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.4451674818992615},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4443266987800598},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.41281864047050476},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3262922167778015},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.298112690448761},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2896274924278259},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26997244358062744},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.18039947748184204},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.07183703780174255},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C53524968","wikidata":"https://www.wikidata.org/wiki/Q7315582","display_name":"Resist","level":3,"score":0.0},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2018.8373273","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2018.8373273","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W809400194","https://openalex.org/W1966149271","https://openalex.org/W1971739315","https://openalex.org/W1997420670","https://openalex.org/W2003208350","https://openalex.org/W2004122330","https://openalex.org/W2032622168","https://openalex.org/W2052163612","https://openalex.org/W2063571983","https://openalex.org/W2088095433","https://openalex.org/W2098330390","https://openalex.org/W2159287000","https://openalex.org/W2161629461","https://openalex.org/W2172169799","https://openalex.org/W3149715914","https://openalex.org/W4230658507","https://openalex.org/W4252122657"],"related_works":["https://openalex.org/W2140942945","https://openalex.org/W2541440459","https://openalex.org/W2050847819","https://openalex.org/W2115795789","https://openalex.org/W2127180614","https://openalex.org/W2000620740","https://openalex.org/W2025251804","https://openalex.org/W1975854055","https://openalex.org/W2032413298","https://openalex.org/W2066716951"],"abstract_inverted_index":{"For":[0],"sub-10":[1],"nanometer":[2],"technology":[3],"nodes,":[4],"multiple":[5],"patterning":[6,35],"technologies":[7],"are":[8,48],"still":[9],"the":[10,15,21,41,49,57,59,86,96,113,117,163],"major":[11],"solutions":[12],"for":[13,54],"pushing":[14],"limit":[16],"of":[17,23,44,98,116,167],"lithography":[18,26,36],"due":[19],"to":[20,134,150],"delay":[22],"next":[24],"generation":[25],"technologies.":[27],"In":[28,56],"this":[29],"paper,":[30],"we":[31,79,121],"propose":[32,128],"a":[33,103,129],"triple":[34],"(TPL)-aware":[37],"router":[38,60],"that":[39,69,81,152],"guarantees":[40],"layout":[42,77,145,153],"decomposability":[43,154],"via":[45,130],"layers,":[46],"which":[47],"layers":[50],"particularly":[51],"requiring":[52],"TPL":[53],"fabrication.":[55],"research,":[58],"does":[61],"not":[62,91],"perform":[63],"simultaneous":[64],"routing":[65,70,109],"and":[66,101,127,165],"coloring":[67],"such":[68],"flexibility":[71],"can":[72],"be":[73],"maximized.":[74],"To":[75,111],"guarantee":[76],"decomposability,":[78],"show":[80,162],"considering":[82],"K4":[83],"avoidance":[84],"in":[85,107],"conflict":[87],"graph":[88,99,105,118,124],"alone":[89],"is":[90,148,155],"sufficient.":[92],"We":[93],"therefore":[94],"adopt":[95],"idea":[97],"isomorphism":[100,119],"construct":[102],"3-uncolorable":[104],"library":[106],"our":[108,158,168],"flow.":[110],"tackle":[112],"high":[114],"complexity":[115],"algorithm,":[120],"use":[122],"several":[123],"reduction":[125],"techniques":[126],"plane":[131],"division":[132],"method":[133],"minimize":[135],"runtime":[136],"overhead.":[137],"Finally,":[138],"an":[139],"optimal":[140],"integer":[141],"linear":[142],"programming":[143],"(ILP)-based":[144],"decomposition":[146],"algorithm":[147],"used":[149],"verify":[151],"ensured":[156],"by":[157],"router.":[159,169],"Experimental":[160],"results":[161],"necessity":[164],"effectiveness":[166]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}