{"id":"https://openalex.org/W2806420140","doi":"https://doi.org/10.1109/vlsi-dat.2018.8373255","title":"28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications","display_name":"28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications","publication_year":2018,"publication_date":"2018-04-01","ids":{"openalex":"https://openalex.org/W2806420140","doi":"https://doi.org/10.1109/vlsi-dat.2018.8373255","mag":"2806420140"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2018.8373255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2018.8373255","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101970595","display_name":"Yichun Wu","orcid":"https://orcid.org/0000-0002-6323-0693"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yi-Chun Wu","raw_affiliation_strings":["Department of Electronics Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066525875","display_name":"Po-Tsang Huang","orcid":"https://orcid.org/0000-0001-8679-2755"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Tsang Huang","raw_affiliation_strings":["International College of Semiconductor Technology, National Chiao Tung University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"International College of Semiconductor Technology, National Chiao Tung University, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101728882","display_name":"Shang-Lin Wu","orcid":"https://orcid.org/0000-0003-3348-0787"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shang-Lin Wu","raw_affiliation_strings":["Department of Electronics Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044258270","display_name":"Sheng-Chi Lung","orcid":null},"institutions":[{"id":"https://openalex.org/I4210112000","display_name":"Faraday Technology (Taiwan)","ror":"https://ror.org/021wyrx76","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210112000"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Sheng-Chi Lung","raw_affiliation_strings":["Faraday Technology Inc., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faraday Technology Inc., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210112000"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081793811","display_name":"Wei-Chang Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210112000","display_name":"Faraday Technology (Taiwan)","ror":"https://ror.org/021wyrx76","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210112000"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Chang Wang","raw_affiliation_strings":["Faraday Technology Inc., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faraday Technology Inc., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210112000"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111568152","display_name":"Wei Hwang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wei Hwang","raw_affiliation_strings":["Department of Electronics Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039359237","display_name":"Ching-Te Chuang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ching-Te Chuang","raw_affiliation_strings":["Department of Electronics Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"59","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8045904040336609},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.7465309500694275},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5780372023582458},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5752934813499451},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5122872591018677},{"id":"https://openalex.org/keywords/queueing-theory","display_name":"Queueing theory","score":0.44793450832366943},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.41722697019577026},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3996203541755676},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34037280082702637},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13932842016220093},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.099254310131073}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8045904040336609},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.7465309500694275},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5780372023582458},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5752934813499451},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5122872591018677},{"id":"https://openalex.org/C22684755","wikidata":"https://www.wikidata.org/wiki/Q847526","display_name":"Queueing theory","level":2,"score":0.44793450832366943},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.41722697019577026},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3996203541755676},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34037280082702637},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13932842016220093},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.099254310131073}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2018.8373255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2018.8373255","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2051161045","https://openalex.org/W2051803964","https://openalex.org/W2086651097","https://openalex.org/W2094648661","https://openalex.org/W2106339466","https://openalex.org/W2138034990","https://openalex.org/W2144289736","https://openalex.org/W2158449659","https://openalex.org/W6680522951"],"related_works":["https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W2172079042","https://openalex.org/W2158323480","https://openalex.org/W2947293127","https://openalex.org/W2618187212","https://openalex.org/W1861585648","https://openalex.org/W2162238921"],"abstract_inverted_index":{"For":[0],"an":[1,75],"energy-limited":[2],"multi-sensing":[3],"platform,":[4],"ultra-low-power":[5,43],"queueing":[6],"design":[7,154],"is":[8,32,46,120],"one":[9],"of":[10],"the":[11,97,152],"critical":[12],"challenge":[13],"to":[14,86,91,106,143],"store":[15],"low-speed":[16],"sensing":[17],"data":[18],"with":[19,112,136],"various":[20],"sampling":[21],"frequencies.":[22],"In":[23],"this":[24],"paper,":[25],"a":[26,38],"near/sub-threshold":[27],"dual-port":[28,54,117],"first-in-first-out":[29],"(FIFO)":[30],"memory":[31,45,119,130],"proposed":[33,153],"for":[34,138],"shared":[35],"queues":[36],"in":[37,122],"unified":[39],"queuing":[40],"architecture.":[41],"This":[42,128],"FIFO":[44,118,129],"designed":[47,105],"and":[48,59,70,80,90,100],"implemented":[49,121],"using":[50],"bit-interleaved":[51],"12T":[52,65],"near-/sub-threshold":[53],"SRAM":[55],"bit-cells,":[56],"write/read-assist":[57],"circuitries,":[58],"adaptive":[60,76],"timing":[61,77],"tracking":[62],"circuits.":[63],"The":[64],"bit-cell":[66],"eliminates":[67],"both":[68],"read":[69,139],"write":[71,93],"half-select":[72],"disturbance.":[73],"Additionally,":[74],"tracing":[78],"circuitry":[79],"negative":[81],"bit-line":[82],"circuits":[83],"are":[84,104],"employed":[85],"against":[87],"PVT":[88],"variation":[89],"enhance":[92],"ability,":[94],"respectively.":[95],"Furthermore,":[96],"self-timed":[98],"pointers":[99],"short":[101],"ripple":[102],"bit-lines":[103],"avoid":[107],"global":[108],"long":[109],"metal":[110],"lines":[111],"large":[113],"loading.":[114],"A":[115],"256\u00d716":[116],"UMC":[123],"28nm":[124],"HKMG":[125],"CMOS":[126],"technology.":[127],"can":[131,147],"be":[132,148],"operated":[133],"at":[134],"0.4V":[135],"10MHz":[137],"operations.":[140],"Moreover,":[141],"up":[142],"60%":[144],"power":[145],"reduction":[146],"achieved":[149],"based":[150],"on":[151],"techniques.":[155]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}