{"id":"https://openalex.org/W4244639592","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939702","title":"Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs","display_name":"Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W4244639592","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939702"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2017.7939702","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939702","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083722186","display_name":"Tetsuo Endoh","orcid":"https://orcid.org/0000-0002-5583-3283"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Tetsuo Endoh","raw_affiliation_strings":["Graduate School of Engineering, Tohoku Univ","JST-ACCEL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Tohoku Univ","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"JST-ACCEL","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5083722186"],"corresponding_institution_ids":["https://openalex.org/I201537933"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.340482,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"e81 c","issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7747259140014648},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.7076418995857239},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6821472644805908},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.6631842851638794},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6113361716270447},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5847440958023071},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.5809007883071899},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5696020126342773},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5592886209487915},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5133897066116333},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5120325684547424},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.46302762627601624},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4625055193901062},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4522866904735565},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.44873908162117004},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.42643308639526367},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40255841612815857},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3405606150627136},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.32971686124801636},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2857072055339813},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.24938100576400757},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1825009286403656}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7747259140014648},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.7076418995857239},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6821472644805908},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.6631842851638794},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6113361716270447},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5847440958023071},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.5809007883071899},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5696020126342773},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5592886209487915},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5133897066116333},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5120325684547424},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.46302762627601624},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4625055193901062},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4522866904735565},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.44873908162117004},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.42643308639526367},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40255841612815857},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3405606150627136},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.32971686124801636},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2857072055339813},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24938100576400757},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1825009286403656},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2017.7939702","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939702","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1521195999","https://openalex.org/W1984119252","https://openalex.org/W1989833718","https://openalex.org/W1991889660","https://openalex.org/W2007389418","https://openalex.org/W2010561573","https://openalex.org/W2021589937","https://openalex.org/W2024856706","https://openalex.org/W2027958074","https://openalex.org/W2049599173","https://openalex.org/W2054328324","https://openalex.org/W2055024370","https://openalex.org/W2060175859","https://openalex.org/W2082365785","https://openalex.org/W2089392392","https://openalex.org/W2089633475","https://openalex.org/W2097793506","https://openalex.org/W2130594732","https://openalex.org/W2132111537","https://openalex.org/W2154590833","https://openalex.org/W2327379784","https://openalex.org/W2342993049","https://openalex.org/W2343026646","https://openalex.org/W2474273396","https://openalex.org/W2580408291","https://openalex.org/W2581156655","https://openalex.org/W2581678330","https://openalex.org/W2582021604","https://openalex.org/W2724700958","https://openalex.org/W2789163685","https://openalex.org/W4241648315","https://openalex.org/W4246826879","https://openalex.org/W6630838423","https://openalex.org/W6674506462","https://openalex.org/W6679622447","https://openalex.org/W6679871945","https://openalex.org/W6733140199"],"related_works":["https://openalex.org/W4232117715","https://openalex.org/W4285257158","https://openalex.org/W2898989424","https://openalex.org/W4238754064","https://openalex.org/W2340699851","https://openalex.org/W2546565930","https://openalex.org/W3006048143","https://openalex.org/W2903040985","https://openalex.org/W2188534734","https://openalex.org/W1981423095"],"abstract_inverted_index":{"Recently":[0],"in":[1,49,72],"semiconductor":[2],"memories":[3,7,11,15,86,89],"such":[4],"as":[5],"embedded":[6,35,85],"(SRAM,":[8],"e-DRAM),":[9],"main":[10,88],"(DRAM)":[12],"and":[13,58,82,87],"storage":[14],"(NAND":[16],"memory),":[17],"it":[18],"is":[19],"becoming":[20],"difficult":[21],"to":[22,46,74],"meet":[23],"the":[24,37,65,77],"target":[25],"performance":[26],"only":[27],"by":[28,93],"scaling":[29],"technologies.":[30],"Especially":[31],"for":[32],"high":[33],"speed":[34,57,66,79],"memories,":[36],"large":[38],"power":[39],"consumption":[40],"brings":[41],"more":[42],"serious":[43],"issues":[44],"due":[45],"rapid":[47],"increase":[48],"memory":[50,70],"capacity":[51],"under":[52],"multi":[53],"core":[54],"MPUs,":[55],"operation":[56,78],"leakage":[59],"current":[60],"of":[61,80,84],"scaled":[62],"CMOS.":[63],"Moreover,":[64],"gap":[67],"between":[68,76],"each":[69],"levels":[71],"addition":[73],"that":[75,83],"MPUs":[81],"have":[90],"expanded":[91],"year":[92],"year.":[94]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}