{"id":"https://openalex.org/W4232052511","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939700","title":"Novel memory hierarchy with e-STT-MRAM for near-future applications","display_name":"Novel memory hierarchy with e-STT-MRAM for near-future applications","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W4232052511","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939700"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2017.7939700","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939700","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111734510","display_name":"Shinobu Fujita","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Shinobu Fujita","raw_affiliation_strings":["Toshiba Corporation, Corporate R&D Center, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Corporate R&D Center, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103020387","display_name":"Hiroki Noguchi","orcid":"https://orcid.org/0000-0003-1659-1389"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroki Noguchi","raw_affiliation_strings":["Toshiba Corporation, Corporate R&D Center, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Corporate R&D Center, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034034258","display_name":"Kazutaka Ikegami","orcid":"https://orcid.org/0000-0002-6234-4568"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazutaka Ikegami","raw_affiliation_strings":["Toshiba Corporation, Corporate R&D Center, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Corporate R&D Center, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111649110","display_name":"Susumu Takeda","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Susumu Takeda","raw_affiliation_strings":["Toshiba Corporation, Corporate R&D Center, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Corporate R&D Center, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032850366","display_name":"Kumiko Nomura","orcid":"https://orcid.org/0000-0003-4185-3723"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kumiko Nomura","raw_affiliation_strings":["Toshiba Corporation, Corporate R&D Center, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Corporate R&D Center, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004388848","display_name":"Keiko Abe","orcid":"https://orcid.org/0000-0001-5844-8199"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Keiko Abe","raw_affiliation_strings":["Toshiba Corporation, Corporate R&D Center, Japan"],"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Corporate R&D Center, Japan","institution_ids":["https://openalex.org/I1292669757"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5111734510"],"corresponding_institution_ids":["https://openalex.org/I1292669757"],"apc_list":null,"apc_paid":null,"fwci":0.43,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67708751,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"50","issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.9146594405174255},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6392624378204346},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.47712066769599915},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4728822112083435},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4094550609588623},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3741900324821472},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3606337308883667},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.13803911209106445},{"id":"https://openalex.org/keywords/political-science","display_name":"Political science","score":0.08474749326705933}],"concepts":[{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.9146594405174255},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6392624378204346},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.47712066769599915},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4728822112083435},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4094550609588623},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3741900324821472},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3606337308883667},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.13803911209106445},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.08474749326705933},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2017.7939700","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939700","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2020675023","https://openalex.org/W2152936426","https://openalex.org/W2180299264","https://openalex.org/W2330052618","https://openalex.org/W4241586847","https://openalex.org/W4249151587"],"related_works":["https://openalex.org/W4403122749","https://openalex.org/W2002108625","https://openalex.org/W2375427054","https://openalex.org/W4231914254","https://openalex.org/W2163958441","https://openalex.org/W2076707939","https://openalex.org/W1576547964","https://openalex.org/W1998340208","https://openalex.org/W4206753316","https://openalex.org/W2015163736"],"abstract_inverted_index":{"Among":[0],"various":[1,31],"kinds":[2,32],"of":[3,33,50,65,83],"nonvolatile":[4],"memory":[5,35,95],"developed,":[6],"spin":[7],"torque":[8],"transfer":[9],"(STT)-MRAM":[10],"has":[11,54],"the":[12,80,94],"highest":[13,18],"write":[14],"access":[15],"speed":[16],"and":[17,41,52,60],"endurance":[19],"(close":[20],"to":[21],"practically":[22],"unlimited":[23],"endurance).":[24],"Hence,":[25],"embedded":[26],"(e-)":[27],"STT-MRAM":[28],"can":[29,89,97],"cover":[30],"working":[34],"applications":[36],"that":[37],"conventionally":[38],"uses":[39],"SRAM":[40,51,84],"e-DRAM.":[42],"In":[43],"advanced":[44],"processors":[45],"or":[46,85],"SoCs,":[47],"static":[48],"power":[49,66,82],"e-DRAM":[53],"been":[55],"increased":[56],"with":[57],"CMOS":[58],"scaling":[59],"becomes":[61],"a":[62],"major":[63],"part":[64],"consumed":[67],"in":[68,79],"those":[69],"semiconductor":[70],"chips.":[71],"Although":[72],"\u201cPower":[73],"gating":[74],"(PG)\u201d":[75],"technique":[76],"enables":[77],"reduction":[78],"leakage":[81],"eDRAM":[86],"effectively,":[87],"it":[88],"be":[90,98],"used":[91],"only":[92],"when":[93],"data":[96],"lost":[99],"while":[100],"application":[101],"is":[102],"not":[103],"running":[104],"(long":[105],"standby":[106],"state;":[107],">1us).":[108]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
