{"id":"https://openalex.org/W2621777950","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939688","title":"Analysis and reduction of SRAM PUF Bit Error Rate","display_name":"Analysis and reduction of SRAM PUF Bit Error Rate","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2621777950","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939688","mag":"2621777950"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2017.7939688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008563407","display_name":"Hirofumi Shinohara","orcid":"https://orcid.org/0000-0001-5589-8397"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Hirofumi Shinohara","raw_affiliation_strings":["Information, Production and Systems Research Center, Waseda University, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Information, Production and Systems Research Center, Waseda University, Fukuoka, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082586585","display_name":"Baikun Zheng","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Baikun Zheng","raw_affiliation_strings":["Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025137710","display_name":"Yanhao Piao","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yanhao Piao","raw_affiliation_strings":["Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114831643","display_name":"Bo Liu","orcid":"https://orcid.org/0000-0003-3704-4595"},"institutions":[{"id":"https://openalex.org/I17056963","display_name":"The University of Kitakyushu","ror":"https://ror.org/03mfefw72","country_code":"JP","type":"education","lineage":["https://openalex.org/I17056963"]},{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Bo Liu","raw_affiliation_strings":["Graduate School of Environmental Engineering, The University of Kitakyushu, Fukuoka, Japan","Information, Production and Systems Research Center, Waseda University, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Environmental Engineering, The University of Kitakyushu, Fukuoka, Japan","institution_ids":["https://openalex.org/I17056963"]},{"raw_affiliation_string":"Information, Production and Systems Research Center, Waseda University, Fukuoka, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100355122","display_name":"Shiyu Liu","orcid":"https://orcid.org/0000-0002-4857-1270"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shiyu Liu","raw_affiliation_strings":["Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5008563407"],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":1.3519,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.8183117,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9764999747276306,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.9595011472702026},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.9414960741996765},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7523161768913269},{"id":"https://openalex.org/keywords/bit-error-rate","display_name":"Bit error rate","score":0.6848812103271484},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6247490644454956},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.5879405736923218},{"id":"https://openalex.org/keywords/physical-unclonable-function","display_name":"Physical unclonable function","score":0.5261037945747375},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49306246638298035},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4763120412826538},{"id":"https://openalex.org/keywords/word-error-rate","display_name":"Word error rate","score":0.4644361436367035},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.45494580268859863},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31768152117729187},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2767021954059601},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18159139156341553},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17548507452011108},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.1369691789150238},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13068649172782898},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.11919251084327698},{"id":"https://openalex.org/keywords/speech-recognition","display_name":"Speech recognition","score":0.11572569608688354},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08914589881896973}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.9595011472702026},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.9414960741996765},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7523161768913269},{"id":"https://openalex.org/C56296756","wikidata":"https://www.wikidata.org/wiki/Q840922","display_name":"Bit error rate","level":3,"score":0.6848812103271484},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6247490644454956},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.5879405736923218},{"id":"https://openalex.org/C8643368","wikidata":"https://www.wikidata.org/wiki/Q4046262","display_name":"Physical unclonable function","level":3,"score":0.5261037945747375},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49306246638298035},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4763120412826538},{"id":"https://openalex.org/C40969351","wikidata":"https://www.wikidata.org/wiki/Q3516228","display_name":"Word error rate","level":2,"score":0.4644361436367035},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.45494580268859863},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31768152117729187},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2767021954059601},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18159139156341553},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17548507452011108},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.1369691789150238},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13068649172782898},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.11919251084327698},{"id":"https://openalex.org/C28490314","wikidata":"https://www.wikidata.org/wiki/Q189436","display_name":"Speech recognition","level":1,"score":0.11572569608688354},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08914589881896973},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2017.7939688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W203309928","https://openalex.org/W609951012","https://openalex.org/W2009564809","https://openalex.org/W2113322447","https://openalex.org/W2116374153","https://openalex.org/W2138874069","https://openalex.org/W6608237463"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W1811213809","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2104885411"],"abstract_inverted_index":{"Reducing":[0],"BER":[1,22,62],"(Bit":[2],"Error":[3],"Rate)":[4],"is":[5,23,55,59],"a":[6,10],"crucial":[7],"problem":[8],"for":[9],"PUF":[11],"(Physical":[12],"Unclonable":[13],"Function)":[14],"in":[15],"the":[16,53,68],"security":[17],"application.":[18],"In":[19],"this":[20],"paper,":[21],"analyzed":[24],"focusing":[25],"on":[26],"two":[27],"major":[28],"factors:":[29],"mismatch":[30,54],"factor":[31,44],"and":[32,48],"noise.":[33],"By":[34],"comparing":[35],"five":[36],"SRAM":[37],"PUFs":[38],"with":[39],"different":[40],"transistor":[41,70],"sizes,":[42],"weight":[43],"of":[45],"load":[46],"pMOS":[47],"driver":[49],"nMOS":[50],"that":[51,61],"determines":[52],"extracted.":[56],"And":[57],"it":[58],"shown":[60],"can":[63],"be":[64],"reduced":[65],"by":[66],"unbalancing":[67],"pMOS/nMOS":[69],"size":[71],"ratio.":[72]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}