{"id":"https://openalex.org/W2622465401","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939648","title":"On designing two-dimensional scan architecture for test chips","display_name":"On designing two-dimensional scan architecture for test chips","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2622465401","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939648","mag":"2622465401"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2017.7939648","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101775144","display_name":"Yu Huang","orcid":"https://orcid.org/0000-0003-2619-4686"},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yu Huang","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020407423","display_name":"Wu-Tung Cheng","orcid":"https://orcid.org/0000-0001-6327-2394"},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wu-Tung Cheng","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210156212"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6193152666091919},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6160102486610413},{"id":"https://openalex.org/keywords/semiconductor-device-fabrication","display_name":"Semiconductor device fabrication","score":0.542384922504425},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5283970236778259},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.429185688495636},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.42375072836875916},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42108890414237976},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3879876136779785},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33893561363220215},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2470836341381073},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23151123523712158}],"concepts":[{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6193152666091919},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6160102486610413},{"id":"https://openalex.org/C66018809","wikidata":"https://www.wikidata.org/wiki/Q1570432","display_name":"Semiconductor device fabrication","level":3,"score":0.542384922504425},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5283970236778259},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.429185688495636},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.42375072836875916},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42108890414237976},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3879876136779785},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33893561363220215},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2470836341381073},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23151123523712158},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2017.7939648","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939648","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2054963492","https://openalex.org/W2058145219","https://openalex.org/W2105880358","https://openalex.org/W2144613846","https://openalex.org/W2144727130","https://openalex.org/W2155829270","https://openalex.org/W2160713416","https://openalex.org/W2168662307","https://openalex.org/W6683494264","https://openalex.org/W6685022266"],"related_works":["https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W4293253840","https://openalex.org/W4378977321","https://openalex.org/W1976168335","https://openalex.org/W4308090481","https://openalex.org/W3211992815","https://openalex.org/W2119025037"],"abstract_inverted_index":{"Real":[0],"silicon":[1,8],"reveals":[2],"a":[3,23,59,70,182,202,230,259,272,278,300],"lot":[4],"about":[5],"how":[6],"new":[7,24,41],"processes":[9],"work,":[10],"so":[11],"test":[12,33,55,78,100,122,161,179,197,212,231,260],"chips":[13,34,87,123,162,180],"are":[14,92,181],"particularly":[15],"helpful":[16],"for":[17,35,195],"the":[18,46,63,82,85,89,118,172,176,196,199,211,297],"semiconductor":[19,27,42],"manufacturers":[20,28],"to":[21,128,166,217,246,277,310],"evaluate":[22],"technology.":[25],"Traditionally,":[26],"relied":[29],"only":[30,58],"on":[31],"SRAM":[32,54,86],"ramping":[36],"up,":[37],"qualifying":[38],"and":[39,48,65,88,115,130,135,150,170,249,267,307],"monitoring":[40],"fabrication":[43],"processes.":[44],"Unfortunately,":[45],"transistor":[47,64],"circuit":[49,66],"geometries":[50,67],"used":[51,93,143],"in":[52,69,144],"an":[53],"chip":[56,79,203,213,232,261],"represent":[57],"small":[60,183],"fraction":[61],"of":[62,105,201,299],"found":[68],"real":[71,90,106],"product":[72],"[BHA98].":[73],"In":[74,175,270,292],"recent":[75],"years,":[76],"logic":[77,99,121,160,178],"that":[80,186,210,238,304],"narrows":[81],"gap":[83],"between":[84],"products":[91],"extensively":[94],"[BHA98]":[95],"[HES07]":[96],"[KAR08].":[97],"The":[98,120,159],"vehicle":[101],"is":[102,208],"more":[103,189,314],"representative":[104],"product,":[107],"but":[108],"may":[109],"not":[110,205],"be":[111,215,224,247,282],"as":[112,117,138,140,188,192],"easily":[113,283],"testable":[114],"diagnosable":[116],"SRAMs.":[119],"must":[124,152,214],"capture":[125],"information":[126],"related":[127],"device":[129],"interconnect":[131],"variability,":[132],"including":[133],"systematic":[134],"random":[136],"variations,":[137],"well":[139],"manufacturing":[141,173,190,220,244,255],"features":[142,191,245],"lithography,":[145],"thermal,":[146],"stress,":[147],"proximity":[148],"effects,":[149],"they":[151],"use":[153,287],"all":[154,219,250,254,264],"potentially":[155],"to-be-used":[156],"library":[157],"cells.":[158],"will":[163],"help":[164],"manufacture":[165],"incorporate":[167],"silicon-accurate":[168],"models":[169],"enhanced":[171],"process.":[174],"past,":[177],"function":[184],"design":[185,229],"contains":[187,242],"possible.":[193],"As":[194],"chips,":[198],"functionality":[200],"does":[204],"matter.":[206],"It":[207,222],"required":[209],"designed":[216],"cover":[218,253],"features.":[221,256],"would":[223],"feasible":[225],"if":[226,285],"we":[227,286,295],"can":[228,281],"with":[233],"many":[234],"scan":[235,240,251,265,279,290,302,312],"cells":[236,252,266,313],"such":[237,258],"each":[239],"cell":[241,280],"some":[243,288],"used,":[248],"Testing":[257],"becomes":[262],"testing":[263,306],"their":[268],"interconnections.":[269],"case":[271],"failure":[273],"occurs,":[274],"diagnosis":[275],"down":[276,309],"achieved":[284],"special":[289],"architectures.":[291],"this":[293],"paper":[294],"present":[296],"concept":[298],"two-dimensional":[301],"architecture":[303],"makes":[305],"diagnose":[308],"defective":[311],"easily.":[315]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":5},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
