{"id":"https://openalex.org/W2621507792","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939647","title":"Robust test pattern generation for hold-time faults in nanometer technologies","display_name":"Robust test pattern generation for hold-time faults in nanometer technologies","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2621507792","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939647","mag":"2621507792"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2017.7939647","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939647","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065281226","display_name":"Yu-Hao Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yu-Hao Ho","raw_affiliation_strings":["Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034494453","display_name":"Yo\u2010Wei Chen","orcid":"https://orcid.org/0000-0002-8096-3469"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yo-Wei Chen","raw_affiliation_strings":["Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010484398","display_name":"Chih\u2010Ming Chang","orcid":"https://orcid.org/0000-0001-8754-7516"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Ming Chang","raw_affiliation_strings":["Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035039603","display_name":"Kai-Chieh Yang","orcid":"https://orcid.org/0000-0002-1141-364X"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kai-Chieh Yang","raw_affiliation_strings":["Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017361488","display_name":"James Chien-Mo Li","orcid":"https://orcid.org/0000-0002-4393-5186"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"James Chien-Mo Li","raw_affiliation_strings":["Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Lab. of Dependable Systems (LaDS), National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5065281226"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.2253,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.47374687,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.9117660522460938},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7063482999801636},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.695819079875946},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.6133493781089783},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.547450840473175},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5381487607955933},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4844377338886261},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.47712254524230957},{"id":"https://openalex.org/keywords/fault-simulator","display_name":"Fault Simulator","score":0.44095349311828613},{"id":"https://openalex.org/keywords/fault-model","display_name":"Fault model","score":0.42026475071907043},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.41244858503341675},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.38402971625328064},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37957262992858887},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30792927742004395},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3067653179168701},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2641812562942505},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08677595853805542},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08233660459518433}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.9117660522460938},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7063482999801636},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.695819079875946},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.6133493781089783},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.547450840473175},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5381487607955933},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4844377338886261},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.47712254524230957},{"id":"https://openalex.org/C2776365744","wikidata":"https://www.wikidata.org/wiki/Q5438149","display_name":"Fault Simulator","level":5,"score":0.44095349311828613},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.42026475071907043},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.41244858503341675},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.38402971625328064},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37957262992858887},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30792927742004395},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3067653179168701},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2641812562942505},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08677595853805542},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08233660459518433},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2017.7939647","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939647","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1849928240","https://openalex.org/W2103288275","https://openalex.org/W2130632823","https://openalex.org/W2163535189","https://openalex.org/W2166455209","https://openalex.org/W2542833283","https://openalex.org/W2621507792","https://openalex.org/W6675422573"],"related_works":["https://openalex.org/W2340957901","https://openalex.org/W4256030018","https://openalex.org/W2147400189","https://openalex.org/W2031110496","https://openalex.org/W2157154381","https://openalex.org/W4253743993","https://openalex.org/W2149684986","https://openalex.org/W2162747415","https://openalex.org/W4248287414","https://openalex.org/W2086978559"],"abstract_inverted_index":{"Hold-time":[0],"faults":[1,38],"are":[2,52,93],"gaining":[3],"attention":[4],"in":[5,46,99],"modern":[6],"technologies":[7],"because":[8],"of":[9,37,44],"process":[10],"variation,":[11],"power":[12],"supply":[13],"noise,":[14],"and":[15,29,56],"etc.":[16],"A":[17,73],"path-based":[18],"hold-time":[19,71,74,115],"fault":[20,57,65,75,101,106,116],"model":[21],"is":[22,39,67,77],"proposed":[23,53],"to":[24,28,41,79],"cover":[25],"short":[26],"paths":[27],"from":[30],"every":[31],"flip-flop.":[32],"In":[33],"addition,":[34],"the":[35,42,47,112],"number":[36,43],"linear":[40],"flip-flops":[45],"circuit.":[48],"Two-timeframe":[49],"circuit":[50],"models":[51],"for":[54,70,114],"ATPG":[55,66,76],"simulation.":[58],"We":[59],"show":[60,88],"that":[61,89],"traditional":[62],"path":[63],"delay":[64],"not":[68],"sufficient":[69],"faults.":[72],"presented":[78],"generate":[80],"robust":[81,100],"test":[82,91,107],"patterns.":[83],"Experiments":[84],"on":[85],"large":[86],"benchmark":[87],"our":[90],"patterns":[92],"42%":[94],"shorter":[95],"while":[96],"38%":[97],"better":[98],"coverage":[102],"than":[103],"1-detect":[104],"stuck-at":[105],"sets.":[108],"The":[109],"results":[110],"justify":[111],"need":[113],"ATPG.":[117]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
