{"id":"https://openalex.org/W1596055821","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114576","title":"A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation","display_name":"A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1596055821","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114576","mag":"1596055821"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2015.7114576","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114576","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077785395","display_name":"Yung-Hui Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yung-Hui Yu","raw_affiliation_strings":["Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","Department of CSIE, National Chiao Tung University, 1001, University Road, Hsinchu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of CSIE, National Chiao Tung University, 1001, University Road, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102778717","display_name":"Po\u2010Hao Wang","orcid":"https://orcid.org/0000-0002-4598-7123"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Hao Wang","raw_affiliation_strings":["Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","Department of CSIE, National Chiao Tung University, 1001, University Road, Hsinchu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of CSIE, National Chiao Tung University, 1001, University Road, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075641814","display_name":"Shang-Jen Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shang-Jen Tsai","raw_affiliation_strings":["Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","Department of CSIE, National Chiao Tung University, 1001, University Road, Hsinchu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of CSIE, National Chiao Tung University, 1001, University Road, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056256074","display_name":"Tien-Fu Chen","orcid":"https://orcid.org/0000-0001-6925-893X"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tien-Fu Chen","raw_affiliation_strings":["Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","Department of CSIE, National Chiao Tung University, 1001, University Road, Hsinchu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of CSIE, National Chiao Tung University, 1001, University Road, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5077785395"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.03322183,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"42","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.8197624683380127},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7446775436401367},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.672099232673645},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5443339943885803},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5343389511108398},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5295451879501343},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48532265424728394},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.48084530234336853},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4489728808403015},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.445030152797699},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4409812390804291},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3844071924686432},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.29939478635787964},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.2649576663970947},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2153901755809784},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1833607256412506},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16766244173049927},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.15264230966567993},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.14605900645256042},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10119667649269104},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06348994374275208}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.8197624683380127},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7446775436401367},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.672099232673645},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5443339943885803},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5343389511108398},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5295451879501343},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48532265424728394},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.48084530234336853},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4489728808403015},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.445030152797699},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4409812390804291},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3844071924686432},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.29939478635787964},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.2649576663970947},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2153901755809784},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1833607256412506},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16766244173049927},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.15264230966567993},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.14605900645256042},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10119667649269104},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06348994374275208},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2015.7114576","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114576","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W90534402","https://openalex.org/W1565403545","https://openalex.org/W1753784006","https://openalex.org/W1984711740","https://openalex.org/W2038721103","https://openalex.org/W2041446224","https://openalex.org/W2073320693","https://openalex.org/W2073922353","https://openalex.org/W2077874318","https://openalex.org/W2093108390","https://openalex.org/W2098931949","https://openalex.org/W2099339734","https://openalex.org/W2103498248","https://openalex.org/W2105597240","https://openalex.org/W2121711421","https://openalex.org/W2132621842","https://openalex.org/W2136444750","https://openalex.org/W2147657366","https://openalex.org/W2157447136","https://openalex.org/W4231535434","https://openalex.org/W4238002809","https://openalex.org/W4244096863","https://openalex.org/W4254558528","https://openalex.org/W6633895739","https://openalex.org/W6668704051","https://openalex.org/W6669789504"],"related_works":["https://openalex.org/W2119312496","https://openalex.org/W4247460323","https://openalex.org/W2537086382","https://openalex.org/W2107909712","https://openalex.org/W2153162275","https://openalex.org/W2079259690","https://openalex.org/W2108986771","https://openalex.org/W789543267","https://openalex.org/W2004965314","https://openalex.org/W2094295436"],"abstract_inverted_index":{"The":[0],"ever-increasing":[1],"transistor":[2],"threshold-voltage":[3],"(Vth)":[4],"variation":[5],"caused":[6],"by":[7],"process":[8],"technologies":[9],"shrink":[10],"brings":[11],"the":[12,26,47,60,68,101,106],"performance":[13,102],"and":[14,34,46,80,91],"reliability":[15,70],"issues":[16],"in":[17,31,43,53,65,76],"SRAM":[18,64],"cells.":[19],"To":[20,57],"keep":[21],"power":[22,62],"limitations,":[23],"scaling":[24],"down":[25],"supply":[27],"voltage":[28],"is":[29],"inevitable":[30],"mobile":[32],"devices":[33],"future":[35],"chips.":[36],"However,":[37],"caches":[38],"become":[39],"susceptible":[40],"even":[41],"fail":[42],"low":[44],"voltages,":[45],"distribution":[48],"of":[49,63,108],"access":[50,110],"latencies":[51],"increases":[52],"new":[54],"technology":[55],"nodes.":[56],"deal":[58],"with":[59],"respectable":[61],"modern":[66],"processors,":[67],"memory":[69],"wall":[71],"poses":[72],"a":[73,89],"major":[74],"challenge":[75],"cache":[77,93,109],"design":[78],"nowadays":[79],"continues":[81],"for":[82,96,115],"years":[83],"to":[84,111],"come.":[85],"This":[86],"thesis":[87],"proposes":[88],"latency-elastic":[90],"fault-tolerant":[92],"not":[94],"only":[95],"fault-tolerant,":[97],"but":[98],"aiming":[99],"at":[100],"issues.":[103],"It":[104],"varies":[105],"latency":[107],"achieve":[112],"better-than-worst-case":[113],"designs":[114],"improving":[116],"performance.":[117]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}