{"id":"https://openalex.org/W1565187077","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114568","title":"Low-noise analog synthesis platform for bio-signal acquisition system","display_name":"Low-noise analog synthesis platform for bio-signal acquisition system","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1565187077","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114568","mag":"1565187077"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2015.7114568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012464226","display_name":"Ying-Chi Lien","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Ying-Chi Lien","raw_affiliation_strings":["Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085934300","display_name":"Ching-Mao Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Mao Lee","raw_affiliation_strings":["Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025918008","display_name":"Chih-Wei Li","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Wei Li","raw_affiliation_strings":["Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050903756","display_name":"Ban-Han Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ban-Han Tsai","raw_affiliation_strings":["Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052798292","display_name":"Chien\u2010Nan Jimmy Liu","orcid":"https://orcid.org/0000-0002-4907-898X"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-Nan Jimmy Liu","raw_affiliation_strings":["Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan ROC","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5012464226"],"corresponding_institution_ids":["https://openalex.org/I22265921"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02586998,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"26","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6843727827072144},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.6585779190063477},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5557766556739807},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5381949543952942},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5378887057304382},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5029937624931335},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5027034282684326},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4351840913295746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2732529044151306},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21269318461418152},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14150747656822205},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10566803812980652}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6843727827072144},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.6585779190063477},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5557766556739807},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5381949543952942},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5378887057304382},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5029937624931335},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5027034282684326},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4351840913295746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2732529044151306},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21269318461418152},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14150747656822205},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10566803812980652},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2015.7114568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.4000000059604645}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W147475332","https://openalex.org/W1980005486","https://openalex.org/W1998752433","https://openalex.org/W2003092850","https://openalex.org/W2007513980","https://openalex.org/W2067870394","https://openalex.org/W2090455930","https://openalex.org/W2102676394","https://openalex.org/W2117811686","https://openalex.org/W2120627534","https://openalex.org/W2126589469","https://openalex.org/W2126996785","https://openalex.org/W2146519106","https://openalex.org/W3147650174","https://openalex.org/W6652144651"],"related_works":["https://openalex.org/W2351655225","https://openalex.org/W1573459484","https://openalex.org/W2361982570","https://openalex.org/W2371541858","https://openalex.org/W3007307084","https://openalex.org/W4253195573","https://openalex.org/W3208739727","https://openalex.org/W2383731669","https://openalex.org/W2020934033","https://openalex.org/W2375192119"],"abstract_inverted_index":{"Because":[0],"the":[1,34,55,73,82,93,107,114],"bio-signals":[2],"are":[3,49],"often":[4],"very":[5],"weak,":[6],"they":[7],"can":[8],"be":[9],"influenced":[10],"by":[11],"noise":[12],"easily":[13],"and":[14,46,77],"become":[15],"hard":[16],"to":[17,32,39,53,69,91,112],"distinguish.":[18],"In":[19],"this":[20,85,110],"paper,":[21],"an":[22],"automatic":[23],"analog":[24,86],"synthesis":[25,87],"platform":[26,88],"is":[27,66,89],"presented":[28],"for":[29],"bio-acquisition":[30],"systems":[31],"generate":[33,54,92,113],"required":[35,56,94,115],"circuits":[36,57,95],"from":[37],"specification":[38],"layout":[40,47],"with":[41,58,98,117],"low-noise":[42],"consideration.":[43],"Process":[44],"variations":[45],"effects":[48],"also":[50,67,105],"simultaneously":[51],"considered":[52],"high":[59],"design":[60,74],"yield.":[61],"Furthermore,":[62],"a":[63],"user-friendly":[64],"GUI":[65],"provided":[68],"help":[70],"users":[71],"complete":[72],"flow":[75],"successfully":[76],"efficiently.":[78],"As":[79],"shown":[80],"in":[81,96],"experimental":[83],"results,":[84],"able":[90],"seconds":[97],"low":[99],"noise.":[100],"The":[101],"chip":[102],"implementation":[103],"result":[104],"verifies":[106],"capability":[108],"of":[109],"tool":[111],"designs":[116],"fabricable":[118],"quality.":[119]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}