{"id":"https://openalex.org/W1507778554","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114534","title":"An impact of process variation on supply voltage dependence of logic path delay variation","display_name":"An impact of process variation on supply voltage dependence of logic path delay variation","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1507778554","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114534","mag":"1507778554"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2015.7114534","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114534","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042142715","display_name":"Shinichi Nishizawa","orcid":"https://orcid.org/0000-0002-1172-7286"},"institutions":[{"id":"https://openalex.org/I39012071","display_name":"Kyoto College of Graduate Studies for Informatics","ror":"https://ror.org/05mzj8a56","country_code":"JP","type":"education","lineage":["https://openalex.org/I39012071"]},{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Shinichi Nishizawa","raw_affiliation_strings":["Graduate School of Informatics, Kyoto University, Kyoto, JAPAN","Graduate School of Informatics, Kyoto University, Yoshida Honmachi, Sakyo-ku, Kyoto 606-8501, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Informatics, Kyoto University, Kyoto, JAPAN","institution_ids":["https://openalex.org/I39012071","https://openalex.org/I22299242"]},{"raw_affiliation_string":"Graduate School of Informatics, Kyoto University, Yoshida Honmachi, Sakyo-ku, Kyoto 606-8501, Japan","institution_ids":["https://openalex.org/I22299242"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022726556","display_name":"Tohru Ishihara","orcid":"https://orcid.org/0000-0002-1650-9958"},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]},{"id":"https://openalex.org/I39012071","display_name":"Kyoto College of Graduate Studies for Informatics","ror":"https://ror.org/05mzj8a56","country_code":"JP","type":"education","lineage":["https://openalex.org/I39012071"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tohru Ishihara","raw_affiliation_strings":["Graduate School of Informatics, Kyoto University, Kyoto, JAPAN","Graduate School of Informatics, Kyoto University, Yoshida Honmachi, Sakyo-ku, Kyoto 606-8501, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Informatics, Kyoto University, Kyoto, JAPAN","institution_ids":["https://openalex.org/I39012071","https://openalex.org/I22299242"]},{"raw_affiliation_string":"Graduate School of Informatics, Kyoto University, Yoshida Honmachi, Sakyo-ku, Kyoto 606-8501, Japan","institution_ids":["https://openalex.org/I22299242"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026865951","display_name":"Hidetoshi Onodera","orcid":"https://orcid.org/0000-0001-5198-0668"},"institutions":[{"id":"https://openalex.org/I39012071","display_name":"Kyoto College of Graduate Studies for Informatics","ror":"https://ror.org/05mzj8a56","country_code":"JP","type":"education","lineage":["https://openalex.org/I39012071"]},{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hidetoshi Onodera","raw_affiliation_strings":["Graduate School of Informatics, Kyoto University, Kyoto, JAPAN","Graduate School of Informatics, Kyoto University, Yoshida Honmachi, Sakyo-ku, Kyoto 606-8501, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Informatics, Kyoto University, Kyoto, JAPAN","institution_ids":["https://openalex.org/I39012071","https://openalex.org/I22299242"]},{"raw_affiliation_string":"Graduate School of Informatics, Kyoto University, Yoshida Honmachi, Sakyo-ku, Kyoto 606-8501, Japan","institution_ids":["https://openalex.org/I22299242"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5042142715"],"corresponding_institution_ids":["https://openalex.org/I22299242","https://openalex.org/I39012071"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.01911563,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.6634283661842346},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6566556692123413},{"id":"https://openalex.org/keywords/delay-line-oscillator","display_name":"Delay line oscillator","score":0.6179346442222595},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6049476265907288},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.5828583836555481},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5821189880371094},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5676480531692505},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.5547225475311279},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5319469571113586},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.5235928297042847},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.503858745098114},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4992835521697998},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.48544222116470337},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.46420249342918396},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.45796918869018555},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42254838347435},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.41949862241744995},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41253340244293213},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.39173972606658936},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.3805815577507019},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.32194966077804565},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2846527099609375},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.2753894329071045},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26953399181365967},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2154669463634491},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.213138610124588},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.1508672833442688}],"concepts":[{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6634283661842346},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6566556692123413},{"id":"https://openalex.org/C26907483","wikidata":"https://www.wikidata.org/wiki/Q5253479","display_name":"Delay line oscillator","level":4,"score":0.6179346442222595},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6049476265907288},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.5828583836555481},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5821189880371094},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5676480531692505},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.5547225475311279},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5319469571113586},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.5235928297042847},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.503858745098114},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4992835521697998},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.48544222116470337},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.46420249342918396},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.45796918869018555},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42254838347435},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.41949862241744995},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41253340244293213},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.39173972606658936},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.3805815577507019},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.32194966077804565},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2846527099609375},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2753894329071045},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26953399181365967},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2154669463634491},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.213138610124588},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.1508672833442688},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2015.7114534","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114534","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7400000095367432}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2029919397","https://openalex.org/W2069217703","https://openalex.org/W2079706534","https://openalex.org/W2081186910","https://openalex.org/W2086447087","https://openalex.org/W6630094435","https://openalex.org/W6670518604"],"related_works":["https://openalex.org/W2171566066","https://openalex.org/W2114346412","https://openalex.org/W2978805287","https://openalex.org/W2302577261","https://openalex.org/W2520586027","https://openalex.org/W2122938731","https://openalex.org/W1965484872","https://openalex.org/W2187496906","https://openalex.org/W2904057067","https://openalex.org/W1507778554"],"abstract_inverted_index":{"Dynamic":[0],"Voltage":[1],"and":[2,30,93],"Frequency":[3],"Scaling":[4],"(DVFS)":[5],"technique":[6],"requires":[7],"accurate":[8],"observation":[9],"of":[10,27,55,69,77,95,100],"critical":[11],"path":[12,31,57,78],"delay":[13,32,58,103],"for":[14,90],"robust":[15],"operation":[16],"under":[17],"aggressive":[18],"supply":[19],"voltage":[20,34,42,53,75,102],"scaling.":[21],"Logic":[22],"paths":[23],"contain":[24],"several":[25],"types":[26],"logic":[28,38],"gates":[29,39],"have":[33,40],"dependences":[35],"because":[36],"different":[37,41],"dependences.":[43],"However,":[44],"it":[45],"is":[46],"not":[47],"well":[48],"investigated":[49],"that":[50],"how":[51],"the":[52,56,67,70,74,91,96,101],"dependence":[54,76,99],"changes":[59],"induced":[60],"by":[61],"process":[62,71,87,97],"variation.":[63],"This":[64],"paper":[65],"describes":[66],"effect":[68],"variation":[72,98],"on":[73],"delay.":[79],"Ring":[80],"Oscillator":[81],"circuits":[82],"fabricated":[83],"in":[84],"65-nm":[85],"CMOS":[86],"are":[88],"used":[89],"evaluation":[92],"analysis":[94],"curves.":[104]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-03-01T08:55:55.761014","created_date":"2025-10-10T00:00:00"}
