{"id":"https://openalex.org/W1583035895","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114523","title":"A 0.6V, 1.3GHz dynamic comparator with cross-coupled latches","display_name":"A 0.6V, 1.3GHz dynamic comparator with cross-coupled latches","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1583035895","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114523","mag":"1583035895"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2015.7114523","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114523","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102059625","display_name":"Bo-Jyun Kuo","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Bo-Jyun Kuo","raw_affiliation_strings":["National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100679035","display_name":"Bowei Chen","orcid":"https://orcid.org/0000-0002-4045-3253"},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]},{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Bo-Wei Chen","raw_affiliation_strings":["Industrial Technology Research Institute, Hsinchu, Taiwan","National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Industrial Technology Research Institute, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]},{"raw_affiliation_string":"National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059558071","display_name":"Chia-Ming Tsai","orcid":"https://orcid.org/0000-0001-8316-4593"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Ming Tsai","raw_affiliation_strings":["National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5102059625"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":1.0928,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.76336602,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.9763580560684204},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7309526205062866},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5426760911941528},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.539587676525116},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5000636577606201},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4947640299797058},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47699764370918274},{"id":"https://openalex.org/keywords/comparator-applications","display_name":"Comparator applications","score":0.4404311776161194},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4400365948677063},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.32987895607948303},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.317751407623291},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.05533328652381897}],"concepts":[{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.9763580560684204},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7309526205062866},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5426760911941528},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.539587676525116},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5000636577606201},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4947640299797058},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47699764370918274},{"id":"https://openalex.org/C121649978","wikidata":"https://www.wikidata.org/wiki/Q17007408","display_name":"Comparator applications","level":4,"score":0.4404311776161194},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4400365948677063},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.32987895607948303},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.317751407623291},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.05533328652381897}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2015.7114523","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114523","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322214","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1977030506","https://openalex.org/W2011479413","https://openalex.org/W2045858890","https://openalex.org/W2046515116","https://openalex.org/W2084760374","https://openalex.org/W2108619270","https://openalex.org/W2128485160","https://openalex.org/W2165468674","https://openalex.org/W6644600904"],"related_works":["https://openalex.org/W2369252356","https://openalex.org/W2744219894","https://openalex.org/W3201763910","https://openalex.org/W3204293969","https://openalex.org/W2136440001","https://openalex.org/W1901843583","https://openalex.org/W1951127657","https://openalex.org/W3161676474","https://openalex.org/W3093575925","https://openalex.org/W3214591077"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,19,67,78],"sub-1V":[4],"dynamic":[5],"comparator":[6,61,95],"with":[7,18],"cross-coupled":[8,15],"latches":[9,16],"at":[10,64,75],"multi-GHz":[11],"operation.":[12],"The":[13,94],"low-voltage":[14],"structure":[17],"separated":[20],"tail":[21],"current":[22],"can":[23],"be":[24],"used":[25],"to":[26,46,72],"optimize":[27],"the":[28,31,34,49,52,60,87,103,107],"speed":[29,40,50],"and":[30,66,77,102],"offset":[32],"in":[33,98],"latched":[35],"stage,":[36],"respectively.":[37],"A":[38],"high":[39],"readout":[41],"circuit":[42,109],"is":[43,96],"also":[44],"proposed":[45],"further":[47],"enhance":[48],"of":[51,91,106],"comparator.":[53],"With":[54],"BER=10":[55],"<sup":[56,112],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[57,113],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">9</sup>":[58],",":[59],"achieves":[62],"143fJ":[63],"3.3GHz":[65],"0.9V":[68],"supply,":[69],"which":[70],"decreases":[71],"only":[73,92],"49fJ":[74],"1.3GHz":[76],"0.6V":[79],"supply.":[80],"Both":[81],"measured":[82],"results":[83],"are":[84],"based":[85],"on":[86],"input":[88],"differential":[89],"voltage":[90],"4.2mV.":[93],"implemented":[97],"65nm":[99],"CMOS":[100],"technology":[101],"chip":[104],"area":[105],"core":[108],"occupies":[110],"265\u03bcm":[111],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[114],".":[115]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-02T15:55:50.835912","created_date":"2025-10-10T00:00:00"}