{"id":"https://openalex.org/W1554048121","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114506","title":"Clock-domain-aware test for improving pattern compression","display_name":"Clock-domain-aware test for improving pattern compression","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1554048121","doi":"https://doi.org/10.1109/vlsi-dat.2015.7114506","mag":"1554048121"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2015.7114506","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114506","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064587514","display_name":"Kun-Han Tsai","orcid":"https://orcid.org/0000-0001-8919-8663"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]},{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["HU","US"],"is_corresponding":true,"raw_author_name":"Kun-Han Tsai","raw_affiliation_strings":["Mentor Graphics Corp., Wilsonville, OR, USA","Mentor Graphics Corp., Wilsonville, OR 97070 USA"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corp., Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]},{"raw_affiliation_string":"Mentor Graphics Corp., Wilsonville, OR 97070 USA","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080960636","display_name":"Janusz Rajski","orcid":"https://orcid.org/0000-0003-2124-447X"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]},{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["HU","US"],"is_corresponding":false,"raw_author_name":"Janusz Rajski","raw_affiliation_strings":["Mentor Graphics Corp., Wilsonville, OR, USA","Mentor Graphics Corp., Wilsonville, OR 97070 USA"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corp., Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]},{"raw_affiliation_string":"Mentor Graphics Corp., Wilsonville, OR 97070 USA","institution_ids":["https://openalex.org/I105695857"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5064587514"],"corresponding_institution_ids":["https://openalex.org/I105695857","https://openalex.org/I4210156212"],"apc_list":null,"apc_paid":null,"fwci":0.646,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.6712625,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8512790203094482},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7178101539611816},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.6654519438743591},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5133540034294128},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5074314475059509},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42285045981407166},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3775229752063751},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3433294892311096},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3371261954307556},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1330873966217041},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.1241360604763031},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09109008312225342}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8512790203094482},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7178101539611816},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.6654519438743591},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5133540034294128},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5074314475059509},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42285045981407166},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3775229752063751},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3433294892311096},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3371261954307556},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1330873966217041},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.1241360604763031},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09109008312225342},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2015.7114506","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2015.7114506","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design, Automation and Test(VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2118204515","https://openalex.org/W2130408546","https://openalex.org/W2143817030","https://openalex.org/W2169632679","https://openalex.org/W4236796643","https://openalex.org/W6681051370"],"related_works":["https://openalex.org/W4285708951","https://openalex.org/W2147986372","https://openalex.org/W2786111245","https://openalex.org/W1979305473","https://openalex.org/W3009953521","https://openalex.org/W4234763172","https://openalex.org/W2992024382","https://openalex.org/W2125317684","https://openalex.org/W1588361197","https://openalex.org/W2161045522"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"an":[3],"integration":[4],"method":[5],"between":[6],"DFT":[7],"and":[8,49],"ATPG":[9,52],"to":[10,44,53,60],"improve":[11],"the":[12,27,41,55,64],"pattern":[13,56],"compression":[14],"by":[15,58],"pulsing":[16],"interactive":[17],"clocks":[18],"(PIC)":[19],"simultaneously.":[20],"The":[21],"proposed":[22],"algorithm":[23],"can":[24],"accurately":[25],"mask":[26],"unreliable":[28],"cross":[29],"clock":[30,35],"domain":[31],"transitions":[32],"for":[33],"any":[34],"skews.":[36],"In":[37],"addition,":[38],"it":[39],"identifies":[40],"required":[42],"flops":[43],"be":[45],"inserted":[46],"hold":[47],"paths,":[48],"combined":[50],"with":[51],"reduce":[54],"count":[57],"up":[59],"39%":[61],"without":[62],"compromising":[63],"test":[65],"quality.":[66]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}