{"id":"https://openalex.org/W1974668623","doi":"https://doi.org/10.1109/vlsi-dat.2014.6834900","title":"An all-digital delay-locked loop for high-speed memory interface applications","display_name":"An all-digital delay-locked loop for high-speed memory interface applications","publication_year":2014,"publication_date":"2014-04-01","ids":{"openalex":"https://openalex.org/W1974668623","doi":"https://doi.org/10.1109/vlsi-dat.2014.6834900","mag":"1974668623"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2014.6834900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2014.6834900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025762419","display_name":"Shih\u2010Lun Chen","orcid":"https://orcid.org/0000-0002-4079-9350"},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Shih-Lun Chen","raw_affiliation_strings":["Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan"],"affiliations":[{"raw_affiliation_string":"Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]},{"raw_affiliation_string":"Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026939108","display_name":"Ming-Jing Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Jing Ho","raw_affiliation_strings":["Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan"],"affiliations":[{"raw_affiliation_string":"Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]},{"raw_affiliation_string":"Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087162426","display_name":"Yuming Sun","orcid":"https://orcid.org/0000-0001-8120-1506"},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Ming Sun","raw_affiliation_strings":["Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan"],"affiliations":[{"raw_affiliation_string":"Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]},{"raw_affiliation_string":"Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045861984","display_name":"Maung Wai Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Maung Wai Lin","raw_affiliation_strings":["Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan"],"affiliations":[{"raw_affiliation_string":"Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]},{"raw_affiliation_string":"Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051789957","display_name":"Jung-Chin Lai","orcid":null},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jung-Chin Lai","raw_affiliation_strings":["Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan"],"affiliations":[{"raw_affiliation_string":"Memory Interface Department, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]},{"raw_affiliation_string":"Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5025762419"],"corresponding_institution_ids":["https://openalex.org/I4210086231"],"apc_list":null,"apc_paid":null,"fwci":0.628,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.71825514,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8831268548965454},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7040512561798096},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5853872895240784},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5686120986938477},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.49800872802734375},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4962640404701233},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.462807834148407},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3503829836845398},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.1168249249458313},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11310887336730957},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10898777842521667}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8831268548965454},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7040512561798096},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5853872895240784},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5686120986938477},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.49800872802734375},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4962640404701233},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.462807834148407},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3503829836845398},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.1168249249458313},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11310887336730957},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10898777842521667},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2014.6834900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2014.6834900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6100000143051147,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1985765219","https://openalex.org/W2012721802","https://openalex.org/W2051099922","https://openalex.org/W2058989901","https://openalex.org/W2081633331","https://openalex.org/W2089395228","https://openalex.org/W2103011017","https://openalex.org/W2143738690","https://openalex.org/W2144572765","https://openalex.org/W2160704142","https://openalex.org/W2161700969","https://openalex.org/W2162025540"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2315668284","https://openalex.org/W2155789024","https://openalex.org/W3213608175","https://openalex.org/W3117675750","https://openalex.org/W2141743053","https://openalex.org/W2109491806","https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W2113057816"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"all-digital":[4],"delay-locked":[5],"loop":[6],"with":[7],"the":[8,32,39,43,46,67,79,87],"novel":[9],"digital":[10,20],"delay":[11,21],"line":[12,22],"for":[13,42],"high-speed":[14],"memory":[15],"interface":[16],"applications.":[17],"The":[18,35,61,72],"proposed":[19,36],"has":[23],"smaller":[24],"tuning":[25,29],"step":[26],"and":[27,50,75,84],"better":[28],"linearity":[30],"than":[31],"prior":[33],"arts.":[34],"ADDLL":[37],"inside":[38],"DDR3":[40],"PHY":[41],"purpose":[44],"of":[45,70,78,90],"90-degree":[47],"phase":[48],"shift":[49],"read":[51],"leveling":[52],"is":[53,63],"fabricated":[54],"in":[55],"a":[56],"40nm":[57],"low-power":[58],"CMOS":[59],"process.":[60],"testchip":[62],"successfully":[64],"verified":[65],"at":[66,86],"data":[68,88],"rate":[69,89],"800~1600Mbps.":[71],"measured":[73],"peak-to-peak":[74],"rms":[76],"jitter":[77],"write":[80],"DQS":[81],"are":[82],"60ps":[83],"10ps":[85],"1600Mbps,":[91],"respectively.":[92]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
