{"id":"https://openalex.org/W1972749955","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212658","title":"Post-bond test techniques for TSVs with crosstalk faults in 3D ICs","display_name":"Post-bond test techniques for TSVs with crosstalk faults in 3D ICs","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W1972749955","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212658","mag":"1972749955"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2012.6212658","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212658","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109093165","display_name":"Yu-Jen Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yu-Jen Huang","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jhongli, Taiwan","Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jhongli, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320#TAB#","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100741015","display_name":"Jingfu Li","orcid":"https://orcid.org/0000-0002-0079-9129"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jin-Fu Li","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jhongli, Taiwan","Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jhongli, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320#TAB#","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102112235","display_name":"Che-Wei Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Che-Wei Chou","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jhongli, Taiwan","Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jhongli, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320#TAB#","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5109093165"],"corresponding_institution_ids":["https://openalex.org/I22265921"],"apc_list":null,"apc_paid":null,"fwci":2.455,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.89266162,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10783","display_name":"Additive Manufacturing and 3D Printing Technologies","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/2203","display_name":"Automotive Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.820642352104187},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.767615020275116},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.653340756893158},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6409637928009033},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6095582246780396},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5657575726509094},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5586004853248596},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.512847900390625},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.46031850576400757},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.43563374876976013},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4336509704589844},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42666077613830566},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.42664816975593567},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.41274142265319824},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18816539645195007},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07704657316207886}],"concepts":[{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.820642352104187},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.767615020275116},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.653340756893158},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6409637928009033},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6095582246780396},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5657575726509094},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5586004853248596},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.512847900390625},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.46031850576400757},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.43563374876976013},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4336509704589844},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42666077613830566},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42664816975593567},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.41274142265319824},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18816539645195007},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07704657316207886},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2012.6212658","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212658","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2013679798","https://openalex.org/W2090396476","https://openalex.org/W2132155220","https://openalex.org/W2141647455","https://openalex.org/W2150113875","https://openalex.org/W2150153665","https://openalex.org/W2156107436","https://openalex.org/W2159112907","https://openalex.org/W2160837841","https://openalex.org/W2171990275","https://openalex.org/W4242674290","https://openalex.org/W6673221304"],"related_works":["https://openalex.org/W1990828594","https://openalex.org/W2016970881","https://openalex.org/W2027159884","https://openalex.org/W2333804548","https://openalex.org/W2534942874","https://openalex.org/W3093450488","https://openalex.org/W2150113875","https://openalex.org/W2016589506","https://openalex.org/W2376702355","https://openalex.org/W4385062230"],"abstract_inverted_index":{"Three-dimensional":[0],"(3D)":[1],"integration":[2],"is":[3,68,108,115],"expected":[4],"to":[5,34],"cope":[6],"with":[7,53,93],"the":[8,48,75,85,89],"difficulties":[9],"faced":[10],"by":[11],"current":[12],"2D":[13],"system-on-chip":[14],"designs":[15],"using":[16],"through":[17],"silicon":[18],"via":[19],"(TSV).":[20],"However,":[21],"coupling":[22],"capacitance":[23],"exists":[24],"between":[25],"two":[26],"neighboring":[27],"TSVs":[28,31,52,67],"such":[29],"that":[30,84],"are":[32],"prone":[33],"crosstalk":[35,54,64],"faults.":[36],"In":[37],"this":[38],"paper,":[39],"we":[40],"propose":[41],"a":[42,98],"builtin":[43],"self-test":[44],"(BIST)":[45],"scheme":[46,73],"for":[47,62,97],"post-bond":[49],"test":[50,60],"of":[51,66,77,88],"faults":[55,65],"in":[56,102],"3D":[57],"ICs.":[58],"A":[59],"algorithm":[61],"testing":[63],"proposed.":[69],"The":[70],"proposed":[71],"BIST":[72,90],"has":[74],"feature":[76],"low":[78],"area":[79,86],"cost.":[80],"Simulation":[81],"results":[82],"show":[83],"overhead":[87],"circuit":[91],"implemented":[92],"90nm":[94],"CMOS":[95],"technology":[96],"512\u00d716":[99],"TSV":[100,105],"array":[101],"which":[103],"each":[104],"cell":[106],"size":[107],"15":[109],"\u00d7":[110],"15\u03bcm":[111],"<sup":[112],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[113],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[114],"6.7%.":[116]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}