{"id":"https://openalex.org/W2154454108","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212640","title":"A novel design methodology for hybrid process 3D-IC","display_name":"A novel design methodology for hybrid process 3D-IC","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2154454108","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212640","mag":"2154454108"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2012.6212640","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212640","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060455058","display_name":"Chien\u2010Lin Huang","orcid":"https://orcid.org/0000-0002-4987-9429"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chien-Lin Huang","raw_affiliation_strings":["Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022084541","display_name":"Nian-Shyang Chang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nian-Shyang Chang","raw_affiliation_strings":["Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080379943","display_name":"Chi\u2010Shi Chen","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chi-Shi Chen","raw_affiliation_strings":["Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100744093","display_name":"Chun\u2010Pin Lin","orcid":"https://orcid.org/0000-0002-3498-1113"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chun-Pin Lin","raw_affiliation_strings":["Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103047746","display_name":"Chien\u2010Ming Wu","orcid":"https://orcid.org/0000-0001-9295-7181"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chien-Ming Wu","raw_affiliation_strings":["Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111606262","display_name":"Chun-Ming Huang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chun-Ming Huang","raw_affiliation_strings":["Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Service Division, Natioanl Chip Implementation Center (CIC), Hsinchu, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2498,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.63195952,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10623","display_name":"Thin-Film Transistor Technologies","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.6959149241447449},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6892690658569336},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.607898473739624},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6045085787773132},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.5780783891677856},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5767051577568054},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5028461813926697},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.5002326965332031},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4948810935020447},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4913982152938843},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4804263114929199},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.47210589051246643},{"id":"https://openalex.org/keywords/design-process","display_name":"Design process","score":0.4513399600982666},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.44234970211982727},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4289761185646057},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4211093485355377},{"id":"https://openalex.org/keywords/process-design","display_name":"Process design","score":0.4131971001625061},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3713483214378357},{"id":"https://openalex.org/keywords/work-in-process","display_name":"Work in process","score":0.20450475811958313},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18339386582374573}],"concepts":[{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.6959149241447449},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6892690658569336},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.607898473739624},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6045085787773132},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.5780783891677856},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5767051577568054},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5028461813926697},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.5002326965332031},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4948810935020447},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4913982152938843},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4804263114929199},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.47210589051246643},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.4513399600982666},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.44234970211982727},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4289761185646057},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4211093485355377},{"id":"https://openalex.org/C55396564","wikidata":"https://www.wikidata.org/wiki/Q3084971","display_name":"Process design","level":3,"score":0.4131971001625061},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3713483214378357},{"id":"https://openalex.org/C174998907","wikidata":"https://www.wikidata.org/wiki/Q357662","display_name":"Work in process","level":2,"score":0.20450475811958313},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18339386582374573},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2012.6212640","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212640","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2042400395","https://openalex.org/W2084861502","https://openalex.org/W2086716781","https://openalex.org/W2122909261","https://openalex.org/W4232892799","https://openalex.org/W4244170660"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W2376726667","https://openalex.org/W2357425846","https://openalex.org/W162881505","https://openalex.org/W2376028644","https://openalex.org/W1965232212","https://openalex.org/W2165817382","https://openalex.org/W3006432396","https://openalex.org/W2038193917","https://openalex.org/W2251104045"],"abstract_inverted_index":{"Three-dimensional":[0],"integrated":[1],"circuit":[2,153,163],"(3D-IC)":[3],"is":[4,46,154],"considered":[5],"to":[6,24,29,52,82,92,136,146,157],"be":[7,25,80,106,165],"the":[8,41,53,85,95,102,116,148,162,168],"most":[9],"promising":[10],"technology":[11],"for":[12,44,98],"modern":[13],"and":[14,131],"future":[15],"electronic":[16,47],"devices":[17],"manufacturing.":[18],"However,":[19],"lots":[20],"of":[21,40,55,87,101,161],"challenges":[22,43],"need":[23],"addressed":[26],"in":[27,167],"order":[28,145],"make":[30],"3D-IC":[31,45,104,141],"technically":[32],"feasible":[33],"as":[34,36],"well":[35],"cost":[37],"effective.":[38],"One":[39],"major":[42],"design":[48,67,118,122,142],"automation":[49],"(EDA)":[50],"due":[51],"lack":[54],"true":[56],"3D":[57,75],"EDA":[58,73],"tools.":[59],"In":[60,144],"this":[61],"paper,":[62],"we":[63,108],"propose":[64],"a":[65,151],"novel":[66],"methodology":[68,78],"which":[69],"makes":[70],"current":[71],"(2D-IC)":[72],"tools":[74],"aware.":[76],"This":[77],"can":[79,105],"applied":[81,103],"3D-ICs":[83],"with":[84],"structure":[86],"2":[88],"tiers":[89],"bonded":[90],"face":[91],"face.":[93],"Since":[94],"process":[96],"node":[97],"each":[99],"tier":[100],"different,":[107],"name":[109],"it":[110],"Hybrid":[111,139],"Process":[112,140],"3D-IC.":[113],"Based":[114],"on":[115],"hierarchical":[117],"methodology,":[119,150],"low":[120],"power":[121],"techniques,":[123],"flip-chip":[124],"physical":[125],"implementation":[126],"methods,":[127],"customized":[128],"cell":[129],"libraries":[130],"scripts":[132],"are":[133],"combined":[134],"together":[135],"build":[137],"up":[138],"methodology.":[143],"verify":[147],"proposed":[149],"real":[152],"designed":[155],"according":[156],"it.":[158],"The":[159],"detail":[160],"will":[164],"described":[166],"following":[169],"paragraphs.":[170]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
