{"id":"https://openalex.org/W2148603542","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212637","title":"High speed DDR2/3 PHY and dual CPU core design for 28nm SoC","display_name":"High speed DDR2/3 PHY and dual CPU core design for 28nm SoC","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2148603542","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212637","mag":"2148603542"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2012.6212637","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212637","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108102149","display_name":"Kevin Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Kevin Ho","raw_affiliation_strings":["Global Unichip Corporation, Taiwan"],"affiliations":[{"raw_affiliation_string":"Global Unichip Corporation, Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101356865","display_name":"Tsung-Yi Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsung-Yi Chou","raw_affiliation_strings":["Global Unichip Corporation, Taiwan"],"affiliations":[{"raw_affiliation_string":"Global Unichip Corporation, Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040355725","display_name":"Po-Kai Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Kai Chen","raw_affiliation_strings":["Global Unichip Corporation, Taiwan"],"affiliations":[{"raw_affiliation_string":"Global Unichip Corporation, Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110252949","display_name":"Dar-Sun Liou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"D. J. Liou","raw_affiliation_strings":["Global Unichip Corporation, Taiwan"],"affiliations":[{"raw_affiliation_string":"Global Unichip Corporation, Taiwan","institution_ids":["https://openalex.org/I4210086231"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5108102149"],"corresponding_institution_ids":["https://openalex.org/I4210086231"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.17013303,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7800803184509277},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6895288228988647},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6485215425491333},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.6090785264968872},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5411564111709595},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.47267040610313416},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.46772563457489014},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.46741247177124023},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4600702226161957},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.436578631401062},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.416866660118103},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34673309326171875},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2596157193183899},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1392209827899933}],"concepts":[{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7800803184509277},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6895288228988647},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6485215425491333},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.6090785264968872},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5411564111709595},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.47267040610313416},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.46772563457489014},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.46741247177124023},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4600702226161957},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.436578631401062},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.416866660118103},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34673309326171875},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2596157193183899},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1392209827899933}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2012.6212637","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212637","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7599999904632568,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1976244802","https://openalex.org/W4293430534","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W2122646225","https://openalex.org/W3140615508","https://openalex.org/W2029945810","https://openalex.org/W1954780666","https://openalex.org/W2216509856"],"abstract_inverted_index":{"As":[0],"DDR":[1],"DRAM":[2,24],"is":[3,66],"running":[4],"at":[5,22],"higher":[6,8],"and":[7,20,29,50,62,82,94,107],"speed,":[9],"the":[10,15,44,56,59,67],"shrinking":[11],"data":[12],"windows":[13],"makes":[14],"timing":[16,34,57],"closure":[17],"in":[18],"setup":[19],"hold":[21],"either":[23],"or":[25],"host":[26],"chip":[27],"more":[28,30],"difficult.":[31],"When":[32],"calculating":[33],"margins":[35],"for":[36],"DDR2/3":[37],"system,":[38],"it":[39],"helps":[40],"to":[41,70,92],"break":[42],"up":[43],"uncertainty":[45],"contributions":[46],"into":[47],"transmitter,":[48],"interconnect":[49],"receiver":[51],"categories.":[52],"Furthermore,":[53],"based":[54],"on":[55],"margins,":[58],"signal":[60],"integrity":[61,64],"power":[63],"analysis":[65],"key":[68],"point":[69],"reach":[71],"success.":[72],"We":[73],"will":[74],"also":[75],"present":[76],"our":[77],"front-end":[78],"experience":[79],"of":[80],"high-speed":[81],"low-power":[83],"28nm":[84],"CPU":[85],"core":[86,97],"hardening,":[87],"from":[88],"top":[89],"RTL":[90],"integration":[91],"synthesis":[93],"DFT.":[95],"This":[96],"includes":[98],"dual-core":[99],"ARM":[100],"Cortex\u2122-A9":[101],"CPU,":[102],"Level":[103],"2":[104],"Cache":[105],"Controller":[106],"Program":[108],"Trace":[109],"Macrocell.":[110]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
